DPU SFC Steering Rules in a Single Accelerated Data Plane
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Solution Overview
Problem
Current SFC architectures lack support for flexible steering rules, configurable and dynamic interface mappings, and network acceleration in a single accelerated data plane, leading to inefficiencies and increased complexity in modern, cloud-centric networks.
Innovation Solution
Implementing hardware-accelerated flexible steering rules, configurable and dynamic SFC interfaces, and a network pipeline abstraction layer (NPAL) on a DPU to process network traffic data in a single accelerated data plane, using a combined set of network rules from different virtual bridges and protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple virtual bridges with distinct steering rules are implemented in traditional SFC architectures, then network service flexibility is improved, but device complexity and operational overhead increase
Solution Approach 1:
The patent combines multiple virtual bridges with distinct steering rules into a single accelerated data plane on the DPU. The hardware acceleration engine processes network traffic data using a unified set of rules that integrates functionality from multiple virtual bridges, eliminating the need to manage separate bridge structures while maintaining service flexibility.
Solution Approach 2:
The single accelerated data plane on the DPU is designed to perform multiple functions simultaneously, handling steering rules from different virtual bridges, protocol processing, and network service delivery through a universal hardware acceleration engine that replaces multiple specialized components.
2Reliability
If traditional middleboxes are deployed for network functions, then network security and performance are improved, but capital investment and operational costs increase
Solution Approach 1:
The patent replaces traditional mechanical middlebox devices with a software-defined, hardware-accelerated solution on the DPU. The acceleration hardware engine implements security and performance functions through programmed rules rather than dedicated physical appliances, reducing infrastructure complexity while maintaining reliability.
Solution Approach 2:
Instead of deploying physical middlebox copies for each network function, the patent uses virtualization to create logical representations of these functions within the single accelerated data plane, allowing multiple virtual bridges and steering rules to coexist without requiring separate physical devices.
3Manufacturing precision
If network traffic is processed through multiple virtual bridges with distinct rules, then steering precision is improved, but processing speed decreases
Solution Approach 1:
The patent replaces software-based rule processing in multiple virtual bridges with hardware-accelerated processing in the DPU's acceleration hardware engine. This substitution maintains steering precision through accurate rule implementation while achieving line-rate processing speeds that software cannot match.
Solution Approach 2:
The patent merges the rule processing functionality of multiple virtual bridges into a single hardware-accelerated data plane, allowing steering rules from different virtual bridges to be processed simultaneously at hardware speed rather than sequentially at software speed.
Data Source
AI summary
Technologies for configuring flexible hardware-accelerated rules in a Service Function Chaining (SFC) architecture are described. A DPU includes an acceleration hardware engine to provide a single accelerated data plane. A processing device within the DPU receives configuration data from a controller and uses this data to generate a first virtual bridge and a second virtual bridge. The first virtual bridge is controlled by a first network service hosted on the DPU and has a first set of network rules. The second virtual bridge has a second set of user-defined network rules. The processing device adds a virtual port between the first and second virtual bridges and generates a combined set of rules based on the first and second network rule sets. The acceleration hardware engine processes network traffic data in the single accelerated data plane using the combined set of network rules.


