DPU Hardware Virtualization for Low-Latency Display Processing

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Solution Overview

Problem

Existing software-based virtualization implementations for display processing suffer from high latency due to hypervisor-based communication with virtual machines, which can lead to issues such as janks and underruns in display processing.

Innovation Solution

A method and apparatus are provided to optimize virtualization components for display processing, allowing for faster interface configuration of hardware resources, enabling multiple virtual machines to control different hardware data paths, and providing secure double data rate access and enhanced inter-VM security.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software-based virtualization with hypervisor is used for display processing, then multiple virtual machines can share hardware resources, but latency increases causing display issues such as janks and underruns

Engineering Contradiction:
Improvemulti-VM resource sharingVSAvoidvirtualization latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent extracts the virtualization management functions from the software hypervisor layer and implements them directly in the display processing hardware. The display processor now natively supports multiple virtual machines through hardware-level virtualization capabilities, eliminating the need for hypervisor-mediated communication and significantly reducing latency while maintaining multi-VM resource sharing

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a hardware-level virtualization interface as an intermediary between virtual machines and display hardware resources. This interface allows VMs to directly access and control display resources through dedicated hardware pathways, bypassing the software hypervisor bottleneck and enabling low-latency display processing

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If hardware resources are shared among multiple virtual machines through software virtualization, then resource utilization improves, but access security and isolation between VMs deteriorates

Engineering Contradiction:
Improvehardware resource utilizationVSAvoidinter-VM security isolation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments display hardware resources into dedicated virtualized components that can be independently allocated to different virtual machines. Each VM receives isolated hardware resource partitions with defined access permissions, enabling secure multi-tenant operation while maintaining high resource utilization through efficient allocation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements differentiated access control policies for different virtual machines, where each VM is granted specific permissions to access particular display hardware resources based on its needs. This local quality approach ensures that each VM receives appropriate security isolation while maintaining optimal resource utilization

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250291618A1Virtualization acceleration in display processing
Publication Date: 2025.09.18 QUALCOMM INC
  • US20250291618A1 patent drawing
  • US20250291618A1 patent drawing
  • US20250291618A1 patent drawing

AI summary

Aspects presented herein relate to methods and devices for display processing including an apparatus, e.g., a DPU. The apparatus may configure a virtualization component for a set of workloads associated with a set of VMs. The apparatus may also execute the set of workloads associated with the set of VMs for a set of virtual queues. The apparatus may also perform at least one of: (1) a mapping of the set of VMs to the set of virtual queues, (2) a security check for an ability of each of the set of VMs to access a set of software registers, or (3) a mapping of each of the set of virtual queues to each of a set of control data paths.