Digital Pulse Width Modulation Resolution Control

The patent dynamically adjusts the PWM period clock frequency based on the required resolution. When high resolution is needed, the system temporarily increases the clock frequency; when lower resolution suffices, it reduces the frequency. This dynamic adaptation allows the system to achieve high output resolution accuracy only when necessary, significantly reducing average power consumption compared to continuously operating at maximum frequency.

The system changes the operating parameters (clock frequency, PWM period) based on the required resolution level. By adjusting these parameters dynamically rather than maintaining fixed high-frequency operation, the patent achieves the desired output resolution accuracy while minimizing power consumption. The controller modifies the PWM period clock frequency parameter according to the specific resolution requirements of the application.

The patent implements a feedback mechanism where the controller monitors the PWM output and adjusts the PWM period clock frequency dynamically to prevent limit cycle oscillations. Instead of relying on continuously high-frequency operation, the system uses feedback to make real-time adjustments to the clock frequency, maintaining output voltage stability while allowing the use of simpler, lower-frequency electronic components.

The system transitions from static high-frequency operation to dynamic frequency adjustment. The PWM period clock frequency is adjusted in real-time based on system conditions and required resolution, enabling the use of simpler electronic components while maintaining stability through adaptive control rather than relying on high-frequency hardware.

Instead of using rapid dithering cycles that create high-frequency current ripples, the patent employs periodic adjustment of the PWM period clock frequency at a much lower rate. The system periodically changes the operating frequency based on resolution requirements, achieving improved effective resolution through temporal averaging while avoiding the harmful high-frequency current ripples associated with dither methods.

The patent changes the PWM period clock frequency parameter periodically rather than using rapid dithering. This slower, more deliberate parameter adjustment achieves resolution improvement through averaging multiple duty cycles at different frequencies, while the lower adjustment rate prevents the generation of significant current ripples that would result from fast dithering.

The patent transforms the fixed PWM period clock frequency into a dynamic parameter that can be adjusted by the controller. The clock frequency is modified based on the required resolution level, allowing the system to achieve higher resolution accuracy when needed without permanently increasing hardware complexity. The dynamic clock management adds minimal control logic while dramatically improving resolution capability.

The system changes the PWM period clock frequency parameter based on operational requirements rather than maintaining a fixed value. This parameter adaptation allows the resolution accuracy to be improved by adjusting the clock frequency to match the required precision level, adding only minimal control complexity while significantly enhancing measurement precision.