Nonvolatile Memory DQ Line Error Margin Configuration

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Flash memory devices experience increased data read errors due to small differences in threshold voltages of memory cells, leading to unreliable data retention and retrieval.

Innovation Solution

A nonvolatile memory device is designed to set different error margins for memory cells based on signal lines, with specific programming states and threshold voltage distributions for each DQ line to enhance data reliability and reduce error correction burdens.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single error margin is used for all memory cells, then the device complexity is low, but the reliability of data read is poor due to small threshold voltage differences

Engineering Contradiction:
Improvedata read reliabilityVSAvoiderror margin configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by assigning different error margins to different DQ lines based on their specific characteristics. Each DQ line is configured with an error margin tailored to its threshold voltage distribution, allowing optimized data read reliability for each line while maintaining overall system manageability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the error margin parameter for different DQ lines to match their respective threshold voltage distributions. By adjusting this critical parameter locally rather than uniformly, the system achieves improved data read reliability without requiring complete redesign of the memory architecture.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If different error margins are set for different DQ lines, then data read reliability improves, but the device complexity increases due to multiple programming states

Engineering Contradiction:
Improvedata output reliabilityVSAvoidprogramming state management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the memory device into multiple DQ line groups, each with its own error margin configuration. This segmentation allows independent optimization of each DQ line's error margin based on its threshold voltage characteristics, improving data output reliability while keeping the complexity manageable through modular organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent modifies the error margin parameter for each DQ line according to its specific threshold voltage distribution. This parameter adjustment enables tailored error correction for each line, achieving superior data output reliability without requiring fundamental changes to the memory cell structure or programming architecture.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If uniform programming is applied to all memory cells, then the manufacturing process is simple, but read errors increase due to varying threshold voltage distributions across different DQ lines

Engineering Contradiction:
Improvethreshold voltage distribution controlVSAvoidprogramming process complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent implements local quality by applying different programming conditions to memory cells associated with different DQ lines. Each DQ line's memory cells are programmed with error margins matched to their specific threshold voltage distributions, achieving precise control over threshold voltages while maintaining a relatively simple manufacturing process through line-specific configurations.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent adjusts programming parameters such as error margins and threshold voltage targets for different DQ lines based on their measured threshold voltage distributions. This parameter customization enables precise threshold voltage control for each line, reducing read errors without requiring completely different manufacturing processes.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11056191B2Nonvolatile memory device having different DQ lines receiving DQ line codes and method of operating nonvolatile memory device using different threshold voltages or error margins
Publication Date: 2021.07.06 SAMSUNG ELECTRONICS CO LTD
  • US11056191B2 patent drawing
  • US11056191B2 patent drawing
  • US11056191B2 patent drawing

AI summary

An operation method of a nonvolatile memory device includes receiving a first DQ signal representing a first data bit from an external device through a first DQ line and receiving a second DQ signal representing a second data bit from the external device through a second DQ line, and programming a first memory cell corresponding to the first DQ line and a second memory cell corresponding to the second DQ line such that the first memory cell has any one of an erase state and a first program state based on the first DQ signal and the second memory cell has any one of the erase state and a second program state based on the second DQ signal. A lower limit value of a threshold voltage distribution corresponding to the second program state is higher than a lower limit value of a threshold voltage distribution corresponding to the first program state.