DQ Pad Layout and Slew Rate Control for Shorter Output Wiring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor memory devices is to reduce the size of data queue (DQ) pads while minimizing the longer wirings between DQ circuits and pads, which lead to higher power consumption due to increased impedance.
Innovation Solution
The semiconductor device design includes a layout where the DQ circuit and pad are positioned to reduce wiring length, with the DQ pad located closer to the DQ circuit, and the use of external resistors for impedance calibration to optimize wiring impedance and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the DQ pad is located far from the DQ circuit, then the area occupied by peripheral circuitries is reduced, but the wiring length increases leading to higher impedance and power consumption
Solution Approach 1:
The patent utilizes multi-layer wiring structures to route signals between the DQ circuit and pad, transitioning from planar two-dimensional routing to three-dimensional spatial routing. This allows the pad to be positioned in a different spatial location without proportionally increasing wiring length, as signals can travel through vertical interconnects across layers rather than only horizontal paths on a single layer.
Solution Approach 2:
The patent introduces external resistors as intermediary components connected between the pad and the DQ circuit. These external resistors serve as impedance matching elements that compensate for the increased wiring impedance caused by longer signal paths, thereby maintaining signal integrity and reducing power consumption despite the increased distance between pad and circuit.
2Area of stationary object
If the DQ pad is located far from the DQ circuit, then the chip area is reduced, but the wiring impedance increases
Solution Approach 1:
External resistors are introduced as intermediary components positioned between the DQ pad and the DQ circuit. These resistors function as impedance matching elements that compensate for the increased wiring impedance resulting from longer signal paths, thereby maintaining signal integrity and electrical reliability despite the increased physical separation between pad and circuit.
Solution Approach 2:
The patent employs multi-layer wiring architectures that enable three-dimensional signal routing. By utilizing vertical interconnects and multiple conductive layers, the design reduces the effective signal path length and impedance even when pads are positioned at the periphery of the chip, thus maintaining electrical reliability while maximizing area utilization.
3Speed
If the DQ circuit size is reduced to improve driving ability, then faster operations are achieved, but the wiring length to pads increases
Solution Approach 1:
The patent implements multi-layer wiring structures that enable vertical signal routing between compact DQ circuits and peripheral pads. This three-dimensional routing approach allows the DQ circuit to be miniimized for high-speed operation while pads remain positioned at chip periphery, as the wiring can traverse through multiple layers rather than requiring long horizontal paths on a single layer.
Solution Approach 2:
External resistors are positioned near the pads to serve as intermediary impedance matching elements. These resistors compensate for the increased wiring impedance resulting from longer signal paths to miniimized DQ circuits, thereby maintaining signal integrity and enabling high-speed operations despite the increased physical distance between compact circuits and pads.
Data Source
AI summary
Apparatuses in data input/output circuits of a semiconductor device are described. An example apparatus includes an output driver and a pre-output driver. The pre-output driver includes: an output terminal coupled to the output driver and provides an output signal to the output driver; an output stage that receives a data signal and provides the output signal to the output terminal responsive, at least in part, to the data signal; and a slew rate control stage coupled to the output stage and controls a current flowing through the output stage. The output stage is disposed between the slew rate control stage and the output terminal.