DQ Pad Reconfigurable Memory Device On-the-fly Mode Switching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional memory devices have fixed DQ pad modes, which cannot be changed during use, requiring separate manufacturing for each mode and limiting user flexibility and increasing production costs.

Innovation Solution

A method and device that allow on-the-fly reconfiguration of DQ pad modes using a DQ organization reconfiguration unit and control signal, utilizing at least one of the M3 and M4 metal layers to minimize chip size overhead, enabling switching between different DQ pad modes such as X32, X16, X8, X4, X2, and X1 modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If DQ pad mode is fixed during manufacturing, then manufacturing precision is improved, but adaptability deteriorates

Engineering Contradiction:
ImproveDQ pad mode configurationVSAvoidDQ pad mode flexibility
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic reconfiguration of DQ pad modes through a mode selection unit that can switch between different DQ pad organizations (X1, X2, X4, X8, X16, X32 modes) during device operation. This allows the memory device to adapt its DQ pad mode based on user commands without requiring separate manufacturing processes for each mode, thereby resolving the contradiction between manufacturing precision and adaptability.

Inventive Principle:
Principle #15Dynamics

2Manufacturing precision

If separate manufacturing is performed for each DQ pad mode, then manufacturing precision is improved, but productivity deteriorates

Engineering Contradiction:
ImproveDQ pad mode configurationVSAvoidproduction efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent creates a universal memory device that can operate in multiple DQ pad modes through a reconfiguration unit and mode selection mechanism. Instead of manufacturing separate devices for each DQ pad mode, a single device design with reconfiguration capabilities serves all mode requirements, significantly improving production efficiency while maintaining consistent manufacturing precision across all modes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If DQ pad mode is changed during use, then adaptability is improved, but device complexity increases

Engineering Contradiction:
ImproveDQ pad mode switchingVSAvoidreconfiguration unit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the DQ pad organization into separable units that can be independently configured. The mode selection unit and reconfiguration unit are structured to handle specific switching operations between different DQ pad modes, breaking down the complex reconfiguration task into manageable segments that reduce overall device complexity while enabling flexible mode changes during operation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10372658B2Method of reconfiguring DQ pads of memory device and DQ pad reconfigurable memory device
Publication Date: 2019.08.06 SAMSUNG ELECTRONICS CO LTD
  • US10372658B2 patent drawing
  • US10372658B2 patent drawing
  • US10372658B2 patent drawing

AI summary

A method and a memory device therefor for reconfiguring a DQ pad organization of the memory device on-the-fly. A DQ organization reconfiguration control unit generates a control signal for reconfiguring the DQ pad organization into a desired mode based on a user command. A DQ organization reconfiguration unit is provided between P DQ pads and memory cell arrays and reconfigures organization P DQ pads on-the-fly in any one among Xi DQ pad modes, where i=1, 2, 4, 8, 16, 32, 64, and 128, based on the control signal. For the reconfiguration of the organization of the DQ pads, a plurality of bus lines for data transfer, being switchable by a control signal, are provided. The bus lines are implemented utilizing at least one of the M3 and M4 metal layers of the memory device.