Per-Pin Memory I/O Termination Calibration for DQ Impedance Matching
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Solution Overview
Problem
Conventional memory device calibration techniques, such as ZQ calibration, fail to account for process variations across DQ pins and non-uniform changes in temperature and voltage, leading to impedance mismatches that cause signal reflections and reduced performance.
Innovation Solution
The implementation of DQ calibration circuitry that adjusts the impedance of output drivers and termination circuits to match those of the host device and data lines, considering individual DQ pin variations and dynamic changes in temperature and voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ZQ calibration is used, then calibration is simple and fast, but impedance mismatches occur due to process variations and temperature/voltage changes
Solution Approach 1:
The patent divides the single global calibration approach into multiple per-pin calibration circuits. Each DQ pin has its own calibration circuit that independently measures and adjusts impedance, allowing individual optimization for each pin rather than using a single global calibration value that cannot account for pin-specific variations.
Solution Approach 2:
The patent implements local calibration by measuring and adjusting impedance characteristics specific to each DQ pin. The calibration circuitry is configured to determine impedance values for individual pins and adjust driver output impedance or termination resistance on a per-pin basis, ensuring each pin is optimized for its specific electrical characteristics and operating conditions.
2Measurement precision
If per-pin calibration is implemented, then impedance matching accuracy improves, but calibration time and complexity increase
Solution Approach 1:
The patent performs impedance calibration during the manufacturing process before the memory device is shipped. The calibration circuits measure impedance characteristics and store calibration values in non-volatile memory or configuration registers, so that when the device is powered on, the calibration is already complete and no additional calibration time is required during operation.
Solution Approach 2:
The calibration circuitry automatically measures impedance values and adjusts driver or termination characteristics without requiring external intervention or manual calibration procedures. The system self-calibrates by comparing measured impedance against target values and automatically applying correction factors to achieve optimal impedance matching.
Data Source
AI summary
Memory devices and systems with per pin input/output termination and driver impedance calibration capabilities, and associated methods, are disclosed herein. In one embodiment, a device apparatus includes circuitry dedicated to an individual DQ pin of the device apparatus. The circuitry can be configured to (i) generate, at least in part, a voltage at the DQ pin based, at least in part, on an impedance internal to a host device electrically connected to the device apparatus and (ii) compare the voltage to a target voltage. Based, at least in part, on the comparison, the circuitry can be configured to adjust a resistance of an output driver and/or a termination circuit of the device apparatus that correspond to the DQ pin to adjust the impedance of the output driver and/or termination circuit to match an impedance associated with a corresponding input/output pin of the host device.