DQ Shift Clock Gating for High-Speed Command Synchronization
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Solution Overview
Problem
High-frequency clock signals in memory devices complicate the synchronization of internal command and clock signals, leading to potential errors in data read and write operations, and existing circuitry for synchronization consumes additional power, which is a concern for power efficiency.
Innovation Solution
The implementation of a delay locked loop clock signal system that selectively transmits the clock signal based on latency and delay indications, using logic gates and flip-flops to automatically synchronize the clock enable signal with incoming commands, reducing power consumption by controlling when the clock signal is transmitted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional circuitry is provided for command and clock synchronization, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by detecting the command signal type (read or write) in advance and generating the clock enable signal before the clock signal is actually needed. The command type detection circuitry identifies whether an incoming command is a read or write command, and the clock enable signal is generated accordingly to enable the delay-locked loop clock signal only when necessary for data output operations, thereby avoiding unnecessary power consumption while maintaining synchronization accuracy.
2Productivity
If clock signal frequency is increased to improve data rate, then productivity is improved, but synchronization difficulty increases
Solution Approach 1:
The patent employs feedback through a delay-locked loop (DLL) mechanism that continuously monitors and adjusts the phase and frequency of the internal clock signal to maintain precise synchronization with the command signals. The DLL circuitry receives the clock signal and generates a delayed version that is fed back to adjust timing, ensuring that even at high frequencies (1 GHz or higher), the clock and command signals remain properly synchronized for multi-data rate memory operations.
Data Source
AI summary
An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal.