Internal DQ Termination for Memory Buffer Signal Integrity
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Solution Overview
Problem
Current memory systems face challenges in maintaining signal integrity due to impedance mismatching during high-speed data transmission between CPUs and memory modules, leading to signal reflection and reduced performance, especially in big data and cloud computing applications.
Innovation Solution
The implementation of a memory module with a data buffer configured for internal data termination and an operating method that controls the internal operation mode to minimize signal reflection by using on-die-termination circuits, ensuring proper termination resistance on both access and internal data paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed data transmission is implemented between CPU and memory module, then data transmission speed is improved, but signal reflection occurs due to impedance mismatching
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the termination resistance value of the ODT circuit based on the operating mode. In normal mode, a first termination resistance value is used, while in self-refresh mode, a second termination resistance value is applied. This dynamic parameter adjustment optimizes signal integrity across different operational states while maintaining high-speed data transmission capability
Solution Approach 2:
The patent implements dynamics by making the termination resistance value changeable according to the memory module's operating mode. The controller selectively controls the ODT circuit to switch between different termination resistance values, enabling the system to adapt to varying signal integrity requirements during normal operation versus self-refresh operation, thus resolving the impedance mismatching issue dynamically
2Reliability
If termination resistance is increased to reduce signal reflection, then signal integrity is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by selectively enabling the ODT circuit only when needed for signal integrity, rather than continuously. The controller activates the ODT circuit with appropriate termination resistance values during specific operating modes (normal mode or self-refresh mode), and can disable or adjust it during other modes, thereby reducing unnecessary power consumption while maintaining signal integrity when required
Solution Approach 2:
The patent implements periodic action by activating the ODT circuit in a periodic manner corresponding to the memory module's operational cycles. The termination resistance is applied during specific operational periods (normal operation or self-refresh) and can be deactivated during other periods, creating a periodic pattern of termination that balances signal integrity requirements with power consumption reduction
Data Source
AI summary
A memory system configured to support internal data (DQ) termination of a data buffer is provided. The memory system includes a first memory module, which is a target memory module accessed by an external device, and a second memory module, which is a non-target memory module not accessed by the external device. The second memory module performs the internal DQ termination on an internal data path during an internal operation mode in which data communication is performed by using the internal data path between internal memory chips. Signal reflection over the internal data path is reduced or prohibited due to the internal DQ termination, and thus, signal integrity is improved.