Multi-rank SDRAM Control Using DQM for Rank Selection
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Solution Overview
Problem
Conventional multi-rank SDRAM configurations face performance degradation due to wait times required to avoid conflicts between ranks and waste unused data bits in SDRAM devices, especially when parity or ECC bit width is narrower than the data port width.
Innovation Solution
The use of DQM (data mask signal) instead of CS# (chip select signal) for rank selection, allowing byte-wise data masking and reducing the number of SDRAM devices needed for parity/ECC, thereby eliminating performance penalties and minimizing waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CS# (chip select signal) is used for rank selection in multi-rank SDRAM configuration, then rank access control is achieved, but wait time is required to avoid conflicts between ranks causing performance degradation
Solution Approach 1:
The patent segments the data mask signal DQM into multiple independent signals (DQM0-DQM7) corresponding to different byte lanes. Each DQM signal can independently mask data for specific byte lanes, allowing simultaneous access to multiple ranks without conflict by selectively masking only the necessary byte lanes during each transaction.
Solution Approach 2:
The patent changes the control parameter from chip select signal CS# to data mask signal DQM for rank selection. This parameter change allows byte-wise masking capability where only specific byte lanes are masked during each memory access, enabling fine-grained control over which rank is accessed without requiring global rank selection that causes conflicts.
2Adaptability or versatility
If conventional CS# based rank control is used, then multi-rank configuration is achieved, but unused data bits remain wasted in SDRAM devices for parity/ECC
Solution Approach 1:
The patent applies local quality by enabling different masking states for different byte lanes within the same SDRAM device. Byte lanes 0-7 can be selectively masked using DQM0-DQM7 signals, allowing the lower-order byte lanes to be used for parity/ECC while upper-order byte lanes remain available for additional rank capacity, optimizing resource utilization at the byte-lane level.
Solution Approach 2:
The patent makes the SDRAM device universally applicable by allowing the same device to serve multiple functions: data storage in some byte lanes and parity/ECC storage in other byte lanes. The byte-wise masking capability enables a single SDRAM device to fulfill both data and parity/ECC roles simultaneously, eliminating the need for separate dedicated parity/ECC devices.
Data Source
AI summary
To provide a multi-rank SDRAM control method and an SDRAM controller that prevent performance degradation and minimize increase in parts count even in a multi-rank SDRAM configuration. A multi-rank SDRAM control method controls a multi-rank SDRAM formed by connecting data buses of multiple SDRAM devices. In each of the multiple SDRAM devices, only a data mask signal for a rank of the SDRAM device, which is to be accessed, is negated, whereby an access to the rank is executed.