DQPSK Parity Verification for Low-Complexity Error Detection
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Solution Overview
Problem
Differential decoding in DQPSK communication systems introduces a Bit Error Rate (BER) penalty due to noise power doubling, and existing methods like multi-symbol phase estimation and non-redundant error correction suffer from complexity or performance issues.
Innovation Solution
A two-stage parity verification procedure is implemented, generating parity and super-parity symbols based on phase differences between DQPSK symbols to detect and correct errors, reducing the differential decoding penalty while maintaining low complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft differential decoding is used to reduce error bursts induced by phase slips, then tolerance against non-linear phase noise is improved, but noise power is doubled causing signal-to-noise ratio degradation
Solution Approach 1:
The decoding process is segmented into two distinct stages: soft differential decoding followed by a parity verification stage. This segmentation allows the system to benefit from the phase noise tolerance of soft differential decoding while adding error detection capability to mitigate the noise power doubling effect, thus resolving the contradiction between reliability improvement and energy loss.
Solution Approach 2:
The parity verification stage provides feedback about detected errors to the decoding process. By calculating parity symbols from received symbols and comparing them against expected values, the system can identify and correct errors introduced by noise power doubling, thereby maintaining signal-to-noise ratio while preserving the tolerance against non-linear phase noise.
2Loss of energy
If multi-symbol phase estimation methods are used to mitigate the differential decoding penalty, then signal-to-noise ratio degradation is reduced, but implementation complexity increases
Solution Approach 1:
The invention extracts the error detection function from the complex multi-symbol phase estimation process by implementing a separate, simpler parity verification stage. This extraction allows the system to address signal-to-noise ratio degradation through error correction rather than through complex phase estimation, thereby reducing implementation complexity while maintaining performance.
Solution Approach 2:
Parity symbols serve as an intermediary mechanism between the received DQPSK symbols and the final decoded output. Instead of directly implementing complex multi-symbol phase estimation, the system uses parity verification as an intermediate step to detect and correct errors, simplifying the overall implementation while effectively mitigating signal-to-noise ratio degradation.
3Device complexity
If non-redundant error correction is used to mitigate the differential penalty, then implementation complexity is reduced, but error correction performance deteriorates
Solution Approach 1:
The parity verification is performed as a preliminary action before final error correction. By calculating and verifying parity symbols early in the decoding process, the system can identify errors that would otherwise go undetected by simple non-redundant error correction, thereby improving error correction performance without significantly increasing implementation complexity.
Solution Approach 2:
The invention adds a new dimension to error correction by introducing parity verification as a separate layer beyond traditional non-redundant error correction. This dimensional addition allows the system to achieve better error correction performance while maintaining low implementation complexity, as the parity verification operates independently from the main decoding path.
Data Source
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AI summary
The invention relates to a method for detecting a parity error in a sequence of DQPSK symbols of a digital transmission system, comprising determining (101) a first demodulated symbol r1 as a parity between a first DQPSK symbol x(n-2) and a second DQPSK symbol x(n-1); determining (102) a second demodulated symbol r2 as a parity between the second DQPSK symbol x(n-1) and a third DQPSK symbol x(n), wherein the first x(n-2), the second x(n-1) and the third x(n) DQPSK symbols are contiguous symbols of the sequence of DQPSK symbols; determining (103) a first parity symbol p1 as a parity between a fourth DQPSK symbol x(n-k) and the third DQPSK symbol x(n); determining (104) a second parity symbol p2 as a parity between a fifth DQPSK symbol x(n-k-m) and the fourth DQPSK symbol x(n-k), wherein the third x(n), the fourth x(n-k) and the fifth x(n-k-m) DQPSK symbols are different and non-contiguous symbols of the sequence of DQPSK symbols; determining (105) a super-parity symbol q1 as a parity between the fifth DQPSK symbol x(n-k-m) and the third DQPSK symbol x(n); and detecting (106) a parity error in the sequence of DQPSK symbols by comparing a combination of the first parity symbol p1 and the second parity symbol p2 against the super-parity symbol q1, wherein a parity between two DQPSK symbols describes a phase difference between the two DQPSK symbols.