DQS Buffer and Comparator Circuit for Stable DDR Data Latching
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Solution Overview
Problem
Conventional DDR SDRAMs face issues with accurate control of the data strobe signal, leading to indeterminate control signal values and potential oscillation, which can result in erroneous data latching due to incorrect timing of the internal digital DQS strobe signal.
Innovation Solution
The proposed solution involves a buffer and control circuitry that receives and buffers the DQS signal, using termination circuits, voltage followers, differential comparators, and programmable output amplifiers to ensure correct signal values during preamble and postamble phases, preventing voltage floating and false detections by selectively clamping and terminating the signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the DQS strobe signal is not driven during Hi-Z state, then power consumption is reduced, but the signal voltage becomes indeterminate and may oscillate causing erroneous data latching
Solution Approach 1:
A voltage follower circuit is introduced as an intermediary between the DQS signal line and the internal digital DQS strobe signal generation. The voltage follower buffers the indeterminate voltage levels during Hi-Z state and provides stable, well-defined voltage levels to the differential comparator, preventing oscillation while allowing the external DQS signal to remain undriven during idle periods.
Solution Approach 2:
A differential comparator is introduced as an intermediary to convert the single-ended DQS signal into a differential internal DQS strobe signal. The comparator actively compares the DQS voltage against a reference and generates clean digital logic levels, eliminating the indeterminate voltage states that would otherwise cause erroneous latching while maintaining power savings during Hi-Z state.
2Speed
If the DQS signal transitions quickly between states, then data transfer speed is improved, but setup and hold time requirements may not be met leading to data capture errors
Solution Approach 1:
The voltage follower circuit is configured to be enabled in advance of critical data transfer operations. By preparing the buffering function beforehand, the circuit ensures that when DQS transitions occur, the signal is already being properly conditioned, allowing fast edges to be accurately captured without violating setup and hold time requirements.
Solution Approach 2:
The differential comparator provides feedback by continuously monitoring the DQS signal level and adjusting the internal digital DQS strobe signal accordingly. This feedback mechanism ensures that even with rapid transitions, the timing relationship between DQS and data signals is maintained within required specifications, preventing capture errors while preserving high-speed operation.
3Reliability
If external termination and clamping circuits are used to stabilize DQS signal, then signal reliability is improved, but device complexity and external component requirements increase
Solution Approach 1:
The voltage follower and differential comparator circuits are integrated directly into the memory device, allowing the device to self-stabilize the DQS signal without requiring external termination or clamping circuits. The internal circuits automatically perform the signal conditioning function that would otherwise require external components, reducing system complexity while maintaining signal reliability.
Solution Approach 2:
The functions of voltage buffering, differential conversion, and timing control are merged into a single integrated circuit block within the memory device. By combining multiple functions that would traditionally require separate external circuits into one unified internal structure, the design achieves signal stability without increasing overall system complexity.
Data Source
AI summary
A method and circuit includes providing at least one conductor for receiving an input signal. A termination circuit and a clamp circuit are coupled to the at least one conductor. The termination circuit is enabled while the clamp circuit remains enabled. The clamp circuit is disabled. After disabling the clamp circuit, while the termination circuit remains enabled, both a first differential comparator and a second differential comparator are enabled. The first differential comparator receives a first differential input signal at a first input and a second differential input signal at a second input. The second differential comparator detects when a difference between the first differential input signal and the second differential input signal is greater than a predetermined value and enables transfer of an output of the first differential comparator to a memory controller.