DQS Calibration Circuit for Multi-Die Memory Timing Failures
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Solution Overview
Problem
The calibration of data strobe signals (DQS) in memory systems becomes challenging as data transfer rates increase, particularly when multiple memory dies are coupled to a single channel, due to timing margin issues and failures in memory controller or input/output drivers.
Innovation Solution
A memory controller with a data strobe signal (DQS) calibration circuit performs N unit DQS calibration operations, including M unit operations in a sequential manner, including normal and conditional modes, to adjust the timing of the DQS signal by varying parameters of a representative memory die identified as causing calibration failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate of memory die is increased, then productivity is improved, but DQS calibration reliability deteriorates
Solution Approach 1:
The patent segments the DQS calibration process into multiple unit calibration operations (N unit operations, where N ≥ 2). Each unit operation calibrates DQS timing for a specific memory die or group of dies. This segmentation allows systematic identification of which specific die causes calibration failure, enabling targeted parameter adjustments for that die while maintaining high data transfer rates across all dies.
Solution Approach 2:
The patent applies parameter changes by adjusting DQS timing parameters specifically for the identified problematic die when calibration fails. The memory controller varies timing parameters (such as DQS phase, polarity, or timing offset) for the specific die causing failure, allowing the system to maintain high data transfer rates while adapting parameters to ensure reliable calibration for each individual die.
2Productivity
If multiple memory dies are coupled to one channel, then productivity is improved, but DQS calibration reliability deteriorates
Solution Approach 1:
The patent segments the calibration process to handle multiple memory dies individually or in controlled groups. By performing N unit calibration operations where each operation targets specific dies, the system can identify which specific die causes calibration failure in a multi-die configuration, enabling precise parameter adjustment for that die while maintaining optimal performance for other dies on the same channel.
Solution Approach 2:
The patent applies partial action by performing calibration operations selectively on specific dies rather than requiring all dies to pass calibration with identical parameters. When calibration fails for a specific die, the system applies parameter adjustments only to that die, allowing the overall multi-die system to maintain high productivity while accommodating individual die variations.
3Measurement precision
If DQS calibration is performed in normal mode for M unit operations, then measurement precision is improved, but upon failure, additional calibration operations are required increasing time consumption
Solution Approach 1:
The patent implements feedback by monitoring the results of each DQS calibration operation and using this information to guide subsequent calibration actions. When calibration fails for a specific die during the N unit operations, the system uses this feedback to identify the problematic die and apply targeted parameter adjustments, avoiding unnecessary repeated calibration attempts on all dies and reducing overall calibration time.
Solution Approach 2:
The patent applies preliminary action by performing M unit calibration operations in normal mode first to establish baseline calibration precision. If calibration succeeds during these preliminary operations, the process terminates early. Only when calibration fails does the system proceed to additional operations with parameter adjustments, thereby minimizing time consumption while maintaining measurement precision.
Data Source
AI summary
In some embodiments of the disclosed technology, a memory controller may include a data strobe signal (DQS) calibration circuit configured to calibrate timing of a data strobe signal (DQS) for a plurality of memory dies by performing N unit DQS calibration operations, wherein N is a natural number, wherein performing the N unit DQS calibration operations includes: performing M unit DQS calibration operations in a normal mode on the plurality of memory dies, wherein M is a natural number smaller than N; upon failure of calibration during the M unit DQS calibration operations in the normal mode, determining a representative memory die of the plurality of memory dies that causes the failure of calibration; and performing N−M unit DQS calibration operations in a conditional mode on the plurality of memory dies by varying parameters associated with the representative memory die of the plurality of memory dies.