Memory Controller DQS Delay Adjustment for Timing Alignment
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Solution Overview
Problem
Current memory training methods in electronic devices are excessively time-consuming, leading to increased bit error rates due to relative timing position offsets between DQS and DQ signals over time, making repeated memory training during the device's working process impractical.
Innovation Solution
A memory training method that adjusts the transmission delay of the DQS signal to align relative timing positions with DQ signals within a short time, allowing for repeated memory training by determining a target DQS transmission delay between maximum and minimum delays, ensuring sufficient timing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current memory training methods are used to align relative timing positions between DQS and DQ, then data transmission accuracy is improved, but training time becomes excessively long
Solution Approach 1:
The patent performs preliminary calibration of DQS transmission delay relative to DQ during manufacturing or initialization. This preliminary action establishes a baseline timing relationship that remains valid under normal operating conditions, eliminating the need for lengthy repeated training procedures and resolving the contradiction between maintaining accuracy and reducing training time
Solution Approach 2:
The patent introduces adjustable delay parameters for the DQS signal that can be dynamically modified based on operating conditions such as temperature and frequency. By changing these parameters in response to environmental variations, the system maintains timing alignment without requiring complete retraining, thus reducing time loss while preserving data transmission accuracy
2Reliability
If memory training is repeatedly performed to correct timing offsets, then data transmission accuracy is maintained, but device operation is disrupted
Solution Approach 1:
The patent implements a self-adjusting mechanism that automatically compensates for timing drift between DQS and DQ signals during normal operation. The system monitors timing margins and autonomously adjusts delay parameters without requiring external intervention or training sequences, thereby maintaining accuracy while avoiding disruptions to device operation
Solution Approach 2:
Instead of continuous or frequent training that would disrupt operation, the patent employs periodic adjustments of delay parameters based on monitored timing conditions. This periodic action maintains synchronization only when necessary, preserving operational continuity while preventing timing drift from degrading data transmission accuracy
3Reliability
If DQS transmission delay is adjusted to align with DQ, then timing margin is improved, but additional control complexity is introduced
Solution Approach 1:
The patent integrates the DQS delay adjustment functionality into the existing memory controller architecture, allowing the same control logic to manage both data transmission coordination and timing alignment. This multi-functionality approach improves timing margin without requiring separate dedicated control mechanisms, thereby limiting the increase in device complexity
Data Source
AI summary
This application provides a memory training method, a memory controller, a processor, and an electronic device. The memory controller keeps transmission delays of N DQs unchanged, adjusts a transmission delay of a DQS, and determines a maximum DQS transmission delay and/or a minimum DQS transmission delay of the DQS when all data carried in the N DQs is correctly transmitted. The memory controller adjusts the transmission delay of the DQS to a target DQS transmission delay between the maximum DQS transmission delay and the minimum DQS transmission delay. The method helps quickly align relative timing positions between the DQS and the N DQs. Therefore, memory training may be repeatedly performed in a working process of the processor, so that the N DQs keep long enough timing margins.