Programmable DQS Delay Circuit for Stable DDR Data Alignment
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Solution Overview
Problem
DDR-SDRAM devices face complexity in writing data due to the narrower valid-data window, requiring precise alignment of the DQS signal with data, which is challenging to maintain stability across varying conditions like process, voltage, and temperature variations.
Innovation Solution
A circuit with a delay locked loop (DLL) system that adjusts the number of cascaded delay elements to maintain a stable delay of the DQS signal, ensuring it is aligned with the data edge by 1/4 of the DDR clock period, using a programmable delay line and master/slave circuitry to account for derating factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple delay line of cascaded basic cell elements is used to delay the DQS signal, then the circuit complexity is low, but the delay stability deteriorates due to process, voltage, and temperature variations
Solution Approach 1:
The patent implements a delay locked loop (DLL) that uses feedback to continuously adjust and compensate for delay variations. The phase detector monitors the phase difference between the DQS signal and the delayed signal, and the up/down counter adjusts the delay line accordingly to maintain stable delay alignment despite process, voltage, and temperature variations.
Solution Approach 2:
The patent transforms the static delay line into a dynamic, adjustable delay mechanism. The programmable delay line allows real-time adjustment of the number of cascaded delay elements based on detected phase differences, enabling the system to adapt to varying operating conditions and maintain optimal delay stability.
2Ease of operation
If the DQS signal is delayed by a fixed amount of time, then the alignment with data center is simple, but the manufacturing precision deteriorates due to variations in derating factors
Solution Approach 1:
The patent dynamically changes the delay parameter by adjusting the number of cascaded delay elements in the programmable delay line. This allows the system to compensate for variations in derating factors such as process variations, voltage changes, and temperature effects, thereby maintaining precise delay alignment with the data center despite manufacturing tolerances.
Solution Approach 2:
The phase detector provides feedback on the actual phase alignment between the DQS signal and the data center, enabling the system to automatically adjust the delay to achieve and maintain precise alignment. This feedback mechanism ensures manufacturing precision by continuously correcting for deviations caused by derating factors.
3Manufacturing precision
If a programmable delay line with multiple cascaded delay elements is used, then the delay alignment precision is improved, but the device complexity increases
Solution Approach 1:
The patent divides the delay function into multiple discrete delay elements arranged in cascade. This segmentation allows the system to achieve precise delay alignment by selectively activating different numbers of delay elements, providing fine-grained control over the delay amount while keeping each individual delay element simple.
Solution Approach 2:
The programmable delay line dynamically reconfigures the number of active delay elements based on the detected phase difference. This dynamic adjustment capability allows the system to achieve high precision delay alignment when needed while maintaining lower complexity during normal operation, as the full delay line is not always required.
Data Source
AI summary
A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to realize said first delay altered by the fraction number of delay elements.