DQS Enable Circuitry for DDR Skew and Jitter Control
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Solution Overview
Problem
In programmable integrated circuits, the variability in circuit board traces between the integrated circuit and memory devices leads to unpredictable data and clock path timing characteristics, resulting in potential skew and jitter that can cause faulty data transfers during memory operations, especially in high-speed DDR transfers.
Innovation Solution
The integration of memory interface circuitry with DQS enable circuitry, including an input buffer, comparator, latching and gating circuit, and counter, which receives differential data strobe signals and generates a gated data strobe signal to synchronize data transfers, ensuring proper timing alignment and reducing skew and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data and clock paths are used in high-speed DDR transfers, then data transfer speed is improved, but timing skew and jitter increase causing faulty data transfers
Solution Approach 1:
A data strobe signal (DQS) is introduced as an intermediary between the memory device and the integrated circuit to synchronize data transfers. The DQS signal is generated by the memory device and used to gate the data signals, ensuring that data is captured at the correct timing intervals. This mediator resolves the timing skew and jitter issues by providing a reference that aligns data sampling with the actual data arrival time, rather than using a separate clock signal that cannot account for path variations.
Solution Approach 2:
The memory device generates its own data strobe signal based on its internal timing, and this signal is used by the integrated circuit to synchronize data capture. The system essentially services itself by using the memory device's own timing characteristics to create the synchronization signal, eliminating the need for an external clock signal that would require separate timing paths. This self-service approach ensures that the strobe signal inherently accounts for the actual data path delays.
2Adaptability or versatility
If circuit board trace lengths vary between integrated circuit and memory devices, then system adaptability is improved, but timing characteristics become unpredictable
Solution Approach 1:
The system dynamically adjusts to different trace lengths by using the actual data strobe signal timing to gate data sampling. Instead of relying on fixed, pre-determined timing characteristics, the system adapts to the actual timing conditions present in each configuration. The DQS enable circuitry dynamically gates the data strobe signal based on the actual arrival timing of data and strobe signals, allowing the system to accommodate varying trace lengths while maintaining reliable data capture.
3Reliability
If data strobe enable circuitry is added to synchronize data transfers, then data transfer reliability is improved, but circuit complexity increases
Solution Approach 1:
The data strobe enable circuitry merges the data strobe signal with the data sampling operation by using the strobe signal to directly gate the data capture process. The latch circuit combines the data input, data strobe signal, and data strobe enable signal into a single synchronized output. This merging approach achieves reliable data transfer without requiring separate, complex synchronization circuits, as the strobe signal itself is used to control the sampling timing.
Data Source
AI summary
An integrated circuit may include memory interface circuitry that is used to communicate with off-chip memory. The memory interface circuitry may include data strobe (DQS) enable circuitry that receives DQS signals from the off-chip memory and that outputs a gated version of the DQS signals. The DQS enable circuitry may include an input buffer, a comparator, a latch, a flip-flop, a counter, and a gating circuit. The input buffer may receive an incoming DQS signal. The comparator may be used to determine when the incoming DQS signal starts to toggle. The latch may be used to control when a gating signal is asserted. The flip-flop controls the counter, which limits the duration that the gating signal is asserted. The gating circuit receives the DQS signal from the buffer and the gating signal and passes the DQS signal through to its output only when the gating signal is asserted.