DQS Pulse Control Circuitry for Memory Write Reliability
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Solution Overview
Problem
Memory devices experience write operation failures due to glitch pulses caused by ringing in the external DQS signal, which can result in incorrect data latching and insufficient timing margins, especially when the pulse width is less than a minimum required width or when the external DQS signal is not held low during the write postamble period.
Innovation Solution
Incorporating DQS pulse control circuitry that receives an external DQS signal and outputs an internal DQS signal with pulse widths greater than or equal to a minimum pulse width, extending or stretching pulses shorter than the minimum width to prevent corruption of valid data and ensure sufficient timing margins for reliable write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the external DQS signal is used directly without pulse width control, then the device complexity is reduced, but write operation reliability deteriorates due to glitch pulses from ringing and insufficient timing margins
Solution Approach 1:
An intermediary DQS pulse control circuit is introduced between the external DQS signal source and the internal DQS signal generation. This circuit includes a delay element and a pulse generation circuit that receives the external DQS signal, delays it, and generates a clean internal DQS signal with controlled pulse width, isolating the sensitive internal circuitry from the noisy external signal while ensuring reliable write operations.
Solution Approach 2:
The DQS pulse control circuit performs preliminary action by pre-processing the external DQS signal before it reaches the internal timing circuits. The circuit anticipates potential glitch pulses from ringing by implementing a minimum pulse width requirement and extending shorter pulses, thereby preventing write operation failures before they occur.
2Measurement precision
If the DQS pulse width is allowed to vary freely, then the ease of operation is improved, but data latching accuracy deteriorates due to insufficient timing margins and glitch pulses
Solution Approach 1:
The DQS pulse control circuit changes the pulse width parameter of the internal DQS signal by implementing a minimum pulse width requirement. The circuit extends any external DQS pulses that are shorter than the minimum width, ensuring that the internal DQS signal always has sufficient pulse width for accurate data latching, thereby transforming the variable pulse width into a controlled parameter with guaranteed minimum duration.
3Reliability
If the external DQS signal is not held low during the write postamble period, then the productivity is improved by reducing idle time, but write operation reliability deteriorates due to glitch pulses from ringing
Solution Approach 1:
The circuit converts the harmful effect of ringing (which causes glitch pulses) into a beneficial outcome by using the DQS pulse control logic to recognize and extend valid pulses. The ringing-induced glitches are filtered out by the minimum pulse width requirement, and the control circuit ensures that even if the external signal is not held low, the internal DQS signal maintains sufficient pulse width for reliable write operations, thereby eliminating the need for extended idle periods.
Data Source
AI summary
Memory with DQS pulse control circuitry is disclosed herein. In one embodiment, a memory device comprises a DQS terminal and circuitry operably coupled to the DQS terminal. The DQS terminal is configured to receive an external DQS signal including a first pulse having a first width. In turn, the circuitry is configured to generate a second pulse based at least in part on the first pulse and output an internal DQS signal including the second pulse. The second pulse can have a second width greater than the first width. In some embodiments, the external DQS signal can further include a third pulse having a third width greater than the second width. In such embodiments, the circuitry can be further configured to generate and output a fourth pulse based at least in part on the third pulse that has a fourth width equivalent to the third width.