DQS Signal Separation Buffers for DRAM Timing Synchronization
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Solution Overview
Problem
The continuous nature of the DQS signal in DRAM often leads to chain effects, necessitating adjustments that are challenging due to its continuous input, which affects the synchronization and timing of data transfer.
Innovation Solution
A signal separation device and method that includes a test circuit, first and second buffers, and command terminals to output test, delay, and command path signals, effectively separating and delaying these signals to meet DRAM specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the DQS signal is kept continuous for normal operation, then data transfer can proceed without interruption, but it becomes difficult to adjust and synchronize the signal timing
Solution Approach 1:
The patent segments the DQS signal path into multiple independent buffers (first buffer, second buffer, third buffer) that can be individually controlled. This allows the continuous DQS signal to be divided into separate controllable segments, enabling timing adjustments without interrupting the overall data transfer operation.
Solution Approach 2:
The patent introduces buffer circuits as intermediary elements between the DQS signal source and the data transfer pathway. These buffers act as mediators that can delay or hold the signal without affecting the continuous operation of the data transfer, thus enabling signal adjustment while maintaining productivity.
2Manufacturing precision
If buffers are added to delay and separate signals for synchronization, then timing accuracy improves, but device complexity increases
Solution Approach 1:
The patent designs buffers that serve multiple functions: they can delay signals, hold signals, and be selectively enabled or disabled. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby achieving precise timing control without proportionally increasing device complexity.
Solution Approach 2:
The patent achieves timing adjustment by changing the operational parameters of existing buffer circuits (enabling/disabling, delaying/holding) rather than adding complex new circuitry. This approach maintains timing accuracy while minimizing increases in device complexity.
Data Source
AI summary
The signal separation device includes a memory. The memory includes a test circuit, a first buffer, and a command terminal. The test circuit is configured to output a test signal. The first buffer is configured to output a first delay signal according to the test signal. The command terminal is configured to output a command path signal according to the test signal and the first delay signal. The first buffer is coupled between the test circuit and the command terminal.