Clock Domain Crossing Synchronizer for Non-Continuous DQS Signals
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Solution Overview
Problem
Semiconductor memory devices experience timing violations due to asynchronous clock domains, particularly when using non-continuous clock signals like DQS clock domain pulses, where traditional synchronizers are unreliable.
Innovation Solution
An internal signal is asserted in response to a command and held HIGH for a predetermined time duration, including the duration of a write operation and additional time, to prevent asynchronous edges and generate a gapless signal, which is then used to create a write enable signal based on both the internal signal and DQS clock pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional synchronizer (chain of flip-flops) is used to synchronize clock domains, then timing violations may be prevented for continuous clock signals, but the synchronizer becomes unreliable when the clock signal is non-continuous (e.g., DQS clock domain pulses)
Solution Approach 1:
The patent changes the operational parameters of the synchronizer by detecting whether the clock signal is continuous or non-continuous, and dynamically adjusting the synchronization method accordingly. For non-continuous clock signals like DQS pulses, the system uses alternative synchronization techniques that do not rely on traditional flip-flop chains, thereby maintaining reliability across different clock signal types.
Solution Approach 2:
The synchronizer is made dynamic by enabling it to adapt its behavior based on the characteristics of the incoming clock signal. The system continuously monitors the clock signal type and switches between different synchronization modes, allowing it to handle both continuous and non-continuous clock signals effectively rather than being fixed to a single synchronization approach.
2Reliability
If clock domains are synchronized using traditional methods, then timing violations may be resolved for continuous clocks, but setup/hold time issues persist with non-continuous clock signals
Solution Approach 1:
The patent introduces an intermediary mechanism that detects the type of clock signal being used and mediates between the clock domain and the synchronization logic. This intermediary component analyzes whether the clock is continuous or non-continuous and routes the signal through appropriate synchronization paths, ensuring that setup and hold time requirements are met for both clock types without direct conflict between the clock domains.
3Reliability
If a synchronizer is used to prevent timing violations, then clock domain crossing may be managed for continuous clocks, but the device complexity increases when handling non-continuous clock signals
Solution Approach 1:
The synchronization system is segmented into multiple specialized components, each optimized for specific clock signal types. Rather than using a single complex synchronizer that must handle all cases, the patent divides the synchronization function into separate handling paths: one for continuous clocks using traditional flip-flop chains, and another for non-continuous clocks using alternative methods. This segmentation reduces the complexity of each individual component while maintaining overall system reliability.
Data Source
AI summary
Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.