DRAM Active Area Width Variation for On-Resistance Reduction
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Solution Overview
Problem
Current DRAMs face challenges in scaling down memory cell size without compromising memory capacity per unit area, leading to high turn-on voltage and large on-resistance, which hinders the development of high-density memories.
Innovation Solution
A semiconductor layout structure for a DRAM array is designed with alternating active areas of different widths, where first active areas have a smaller width than second active areas, and bit lines intersect these areas, reducing fabrication difficulties and improving device performance by varying charge storage capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is scaled down to increase circuit density, then memory capacity per unit area is improved, but turn-on voltage increases and on-resistance becomes large
Solution Approach 1:
The patent applies local quality by creating active areas with different widths (first active areas with width W1 and second active areas with width W2, where W1 < W2) to provide different charge storage capabilities in different locations. This allows the memory device to have varied on-resistance characteristics across the array, enabling better performance optimization for specific memory cell requirements while maintaining high density through the alternating pattern layout.
2Productivity
If feature size is reduced to increase circuit density, then more components can be accommodated, but fabrication process limits are exceeded and manufacturing becomes difficult
Solution Approach 1:
The patent segments the active areas into two distinct types (first active areas and second active areas) with different widths, arranged in an alternating pattern. This segmentation allows the fabrication process to work with larger, more manageable feature sizes while still achieving high circuit density through the varied layout pattern, rather than requiring uniform miniaturization of all features.
Solution Approach 2:
The patent introduces asymmetry by using non-uniform active area widths (W1 and W2) in the memory array layout. This asymmetric design breaks the traditional uniform pattern, allowing for optimized charge storage and reduced on-resistance without requiring proportional scaling of all features, thereby maintaining ease of manufacture while achieving high density.
3Ease of manufacture
If uniform active areas are used throughout the memory array, then fabrication is simplified, but charge storage capability and performance are limited
Solution Approach 1:
The patent implements local quality by assigning different widths to different active areas (first active areas with width W1 and second active areas with width W2), creating spatial variation in charge storage capability. This allows regions with higher charge storage requirements to use wider active areas while maintaining overall fabrication simplicity through the regular alternating pattern, thus balancing manufacturing ease with enhanced performance.
Data Source
AI summary
A semiconductor layout structure for a dynamic random access memory (DRAM) array, comprising an isolation structure and a plurality of active areas situated in a semiconductor substrate, each of the active areas extending along a length-wise central axis. The isolation structure is situated among the active areas. The active areas are arranged in an array and comprise a plurality of first active areas and a plurality of second active areas. The first active areas are arranged along a first length-wise direction of the active areas. The second active areas are arranged along a second length-wise direction of the active areas. The first active areas are parallel and adjacent to the second active areas, and the first and second active areas are alternately distributed in a direction of word-lines. The first active area having a first width smaller than a second width of the second active area.