DRAM Bank Masking for Selective Refresh Operations

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Solution Overview

Problem

In dynamic random access memory (DRAM) devices, the periodic refresh operation affects the average time interval between refresh commands, leading to inefficiencies in memory controller operations, as all rows are subjected to refresh, which can be wasteful and increase the number of refresh commands needed.

Innovation Solution

A method and apparatus for a memory device that masks certain banks in response to a mode register writing command, allowing only unmasked banks to perform refresh operations, with specific command and signal conditions determining which banks are masked or unmasked, thereby optimizing refresh operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If refresh operation is performed on all rows in all banks, then data integrity is maintained, but the number of refresh commands increases and average time interval between refresh commands decreases

Engineering Contradiction:
Improvedata integrityVSAvoidaverage time interval between refresh commands
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory device is divided into multiple banks, and the refresh operation is segmented to be performed selectively on unmasked banks rather than all banks. This segmentation allows the system to maintain data integrity in active banks while reducing the overall refresh command frequency across the entire memory device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of performing refresh operations on all banks (excessive action), the system performs partial refresh operations only on unmasked banks that contain active data. This partial action approach maintains necessary data integrity while reducing the total number of refresh commands issued.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If refresh operation is performed on all rows, then all data is refreshed, but this causes increased number of refresh commands and reduced memory controller efficiency

Engineering Contradiction:
Improvedata refresh completenessVSAvoidmemory controller efficiency
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The mask register enables different quality states for different banks - masked banks are excluded from refresh operations while unmasked banks receive refresh operations. This local differentiation allows the memory controller to optimize its operation by focusing refresh resources only on banks that require them, improving overall controller efficiency.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system performs partial refresh actions only on unmasked banks rather than refreshing all banks. This partial action maintains adequate data refresh for active regions while reducing the burden on the memory controller, thereby improving ease of operation.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If mask register is used to select masked banks, then refresh operations are reduced, but bank selection complexity increases

Engineering Contradiction:
Improverefresh operation reductionVSAvoidbank selection mechanism
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The mask register creates a simplified copy or representation of bank selection states, where each bit in the mask register corresponds to a specific bank. This copying mechanism allows the memory controller to efficiently determine which banks should be refreshed without complex selection logic, as the mask register provides a direct mapping of refresh eligibility.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS8737153B2Memory device, method of operating the same, and apparatus including the same
Publication Date: 2014.05.27 SAMSUNG ELECTRONICS CO LTD
  • US8737153B2 patent drawing
  • US8737153B2 patent drawing
  • US8737153B2 patent drawing

AI summary

A method of operating a memory device includes masking at least one bank among a plurality of banks in response to a mode register writing command; and performing a refresh operation on a plurality of rows in one of unmasked banks in response to a first per-bank refresh command.