DRAM Bank Segmentation for Burst Input Latency
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Solution Overview
Problem
In communication input/output apparatuses, the storage capacity required in the memory increases with the number of output systems, leading to latency in DRAM access due to row address activation, which deteriorates effective throughput and increases power consumption, especially when handling burst inputs of short frame data.
Innovation Solution
A communication input/output apparatus with a DRAM data memory that uses a write pointer for each bank, a queue control memory to manage active row addresses, and a DRAM access unit that selects a bank with an active flag for writing, activating the row address only when necessary to reduce latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM is used to increase storage capacity for multiple output systems, then storage capacity is improved, but access latency increases due to row address activation requirements
Solution Approach 1:
The DRAM is divided into multiple banks, and the patent implements bank-level segmentation with independent row address activation for each bank. This allows parallel access to different banks, reducing overall access latency while maintaining large storage capacity across multiple queues for different output systems.
Solution Approach 2:
The patent introduces a bank dimension to the memory access structure, organizing queues across multiple banks rather than using a single linear address space. This dimensional organization enables simultaneous activation of different row addresses in different banks, effectively converting a sequential access bottleneck into a parallel access architecture.
2Adaptability or versatility
If row address activation is performed frequently to access different row addresses in the same bank, then data access flexibility is improved, but power consumption increases
Solution Approach 1:
By segmenting the memory into multiple banks with independent row address activation, the patent allows the system to maintain data access flexibility while reducing power consumption. When multiple queues need to be accessed, the system can activate row addresses in different banks simultaneously rather than sequentially, reducing the total number of activation operations required.
Solution Approach 2:
The patent changes the memory access parameter from single-bank sequential activation to multi-bank parallel activation. This parameter change allows the system to maintain high adaptability for accessing different queues while reducing the frequency of row address activation events, thereby lowering power consumption.
3Adaptability or versatility
If multiple queues are implemented for different output destinations, then output system versatility is improved, but memory access complexity increases
Solution Approach 1:
The patent segments the memory structure into multiple banks, with each bank capable of handling multiple queues. This segmentation provides a natural organizational structure for managing multiple output destinations while maintaining relatively simple access patterns within each bank, reducing overall access complexity compared to a monolithic memory structure.
Data Source
AI summary
In a recording device, a data memory including a DRAM having a write pointer for each of banks, and a queue control memory that stores an active flag is provided. When frame data is written into a write-target queue, a bank for which an active flag indicates an activated state is selected as a write-target bank among the banks to write the frame data, and if there is no bank for which an active flag indicates an activated state, a bank for which an active flag indicates a deactivated state is selected as a write-target bank, a row address of a write pointer of the bank is activated, and thereafter the frame data is written.