DRAM Bit Line Gate Structure Contact Resistance Reduction
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face high contact resistance issues at the interface between the polysilicon layer and the metal stack, limiting their performance and efficiency.
Innovation Solution
A bit line gate structure is developed where the maximum implanting concentration of the polysilicon layer is positioned at the interface with the metal stack, achieved through forming a sacrificial layer and performing an implantation process or plasma doping, followed by removing the sacrificial layer and depositing a metal stack, thereby reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional polysilicon layer structure is used without optimized doping, then the manufacturing process is simpler, but the contact resistance at the interface with the metal stack is high
Solution Approach 1:
The patent applies preliminary action by performing the implantation process on the sacrificial layer before the metal stack is formed. This allows the polysilicon layer to be pre-doped with maximum concentration at the interface region where contact resistance needs to be minimized, before the metal stack is deposited. The sacrificial layer serves as a template to guide the doping profile creation in advance.
Solution Approach 2:
The sacrificial layer acts as an intermediary medium during the doping process. By implanting dopants through the sacrificial layer into the polysilicon layer, the patent achieves a controlled doping profile with maximum concentration at the interface. The sacrificial layer is later removed, but its temporary presence enables precise doping profile formation that would be difficult to achieve directly.
2Reliability
If the polysilicon layer has uniform doping concentration, then the manufacturing process is simpler, but the contact resistance at the metal stack interface remains high
Solution Approach 1:
The patent applies local quality by creating a non-uniform doping concentration distribution in the polysilicon layer. The maximum dopant concentration is localized specifically at the interface with the metal stack, while other regions have lower concentrations. This localized high doping region reduces contact resistance precisely where it is most critical, without requiring high doping throughout the entire layer.
Solution Approach 2:
The patent changes the doping concentration parameter spatially within the polysilicon layer. By controlling the implantation process through the sacrificial layer, the dopant concentration varies from maximum at the metal stack interface to lower values in other regions. This parameter variation optimizes electrical contact properties without compromising other functional requirements of the polysilicon layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces contact resistance and allows for a thinner bit line gate structure, enhancing the performance and efficiency of DRAM devices.
Implementation Method 1
An implantation process is performed on the sacrificial layer and the polysilicon layer
Implementation Method 2
A plasma doping process is performed on a surface of the polysilicon layer
Data Source
AI summary
A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.