DRAM Bit Line Switches for Self-Refresh Current Reduction
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Solution Overview
Problem
Dynamic random access memory (DRAM) experiences high self-refresh current during standby mode, leading to excessive power consumption, which existing methods attempt to mitigate by reducing bit line word lines, but at the cost of increased memory chip area.
Innovation Solution
Incorporating switch elements on bit lines that are controlled by specific control signals to manage their conduction states during self-refresh periods, thereby reducing the equivalent capacitance and current consumption without expanding the chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the number of word lines coupled to bit lines is decreased to reduce equivalent capacitance, then self-refresh current is reduced, but memory chip area is increased
Solution Approach 1:
The bit lines are segmented into multiple groups, with each group coupled to a different sense amplifier circuit. Switch elements are selectively activated based on which group needs to be refreshed, allowing partial operation rather than requiring all word lines to remain connected. This segmentation enables reduced capacitance loading while maintaining full memory coverage.
Solution Approach 2:
The patent implements dynamic control of switch elements that connect bit lines to sense amplifier circuits. During self-refresh mode, only the necessary subset of switch elements is activated based on which bit line groups require refreshing. This dynamic activation reduces the equivalent capacitance compared to having all switch elements permanently connected, thereby reducing self-refresh current without requiring fewer word lines.
2Use of energy by moving object
If switch elements are added to control bit line conduction, then self-refresh current is reduced, but device complexity increases
Solution Approach 1:
The switch elements serve multiple functions: they act as access switches during normal read/write operations and as selection switches during self-refresh mode. The sense amplifier circuits also serve dual purposes by handling both data I/O and self-refresh operations for their associated bit line groups. This multi-functionality reduces the need for separate dedicated components.
Solution Approach 2:
The memory controller automatically manages the activation of switch elements during self-refresh mode based on pre-defined refresh schedules for different bit line groups. The system self-regulates which switch elements are active without requiring external intervention or complex control logic, as the refresh pattern is determined by the memory controller's internal timing and addressing logic.
Data Source
AI summary
A dynamic random access memory including a memory cell array and a memory controller is provided. The memory cell array includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. The memory controller is coupled to the memory cells via the bit lines and the word lines. The memory controller is configured to perform a self-refresh operation on the memory cell array during a self-refresh period. Each of the bit lines includes a switch element. The memory controller controls a part of the switch elements to be conducted and a part of the switch elements not to be conducted during the self-refresh period.