DRAM Buried Bit Line Side Contact Pitch Relaxation
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Solution Overview
Problem
Conventional dynamic random access memory (DRAM) designs face challenges such as lithography difficulty, small active contact area, poor write recovery time, high bit line parasitic capacitance, and poor bit line sensing margin due to angled active area layouts, which tighten the pitch between active areas and increase parasitic capacitance.
Innovation Solution
The DRAM design features a substrate with isolation structures, word lines, bit line contacts, and buried bit lines, where the buried bit lines are parallel to the active regions and connected via bit line side contacts, relaxing the pitch and allowing for a larger active area, thus improving lithography friendliness and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If angled active area layout is used to connect capacitor to active area, then connection is achieved, but pitch between active areas is tightened causing lithography difficulty
Solution Approach 1:
The patent inverts the conventional connection approach by using bit line side contacts to connect buried bit lines to active areas, rather than using angled active area layouts. This inversion allows the bit lines to run parallel to active areas, relaxing the pitch constraints and improving lithography friendliness while maintaining proper electrical connections.
Solution Approach 2:
The patent introduces bit line side contacts that extend in a lateral dimension alongside the active areas, rather than requiring vertical or angled penetration. This dimensional change allows for relaxed pitch between active areas while maintaining electrical connectivity through the side contact structure.
2Object-generated harmful factors
If angled active area layout is used, then capacitor connection is achieved, but bit line parasitic capacitance increases
Solution Approach 1:
The patent inverts the conventional connection approach by using bit line side contacts to connect buried bit lines to active areas, rather than using angled active area layouts. This inversion allows the bit lines to run parallel to active areas, relaxing the pitch constraints and improving lithography friendliness while maintaining proper electrical connections.
3Reliability
If angled active area layout is used, then capacitor connection is achieved, but bit line sensing margin deteriorates
Solution Approach 1:
The patent inverts the conventional connection approach by using bit line side contacts to connect buried bit lines to active areas, rather than using angled active area layouts. This inversion allows the bit lines to run parallel to active areas, relaxing the pitch constraints and improving lithography friendliness while maintaining proper electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the design and performance of DRAM by reducing bit line parasitic capacitance and improving bit line sensing margin, resulting in a more efficient and reliable memory cell.
Implementation Method 1
Liners and spacers are formed above the isolation structures and on one sidewall of the trenches through an angled ion implantation process
Data Source
AI summary
A dynamic random access memory (DRAM) is provided. The DRAM comprises a substrate, a plurality of isolation structures, a plurality of word lines, a plurality of bit line contacts and a plurality of buried bit lines. The isolation structures are located in the substrate and defines a plurality of active regions extending along a first direction. The word lines are located in the substrate and are extending along a second direction, the second direction intersects with the first direction. The bit line contacts are located above the isolation structures, wherein each of the bit line contacts have a diffusion region that defines a bit line side contact. The buried bit lines are located above the bit line contacts and are connected to the active region via the bit line side contact, the buried bit lines are extending along the first direction and is parallel with the plurality of active regions.