DRAM Capacitor Support Layer Carbon Gradient Etching
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Solution Overview
Problem
The challenge in increasing the density of DRAM memory cells is compounded by the difficulty in forming electrode layers with high aspect ratios, which leads to etching damage and reduced manufacturing yield due to the complexity of capacitor structure design.
Innovation Solution
A semiconductor memory device is developed with a first support layer having varying carbon concentrations, where the bottom portion has a higher carbon concentration than the top portion, allowing for differential etching rates during the etching process to mitigate damage and enhance yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacitor structure extends upwards to increase electrode area, then the capacitance requirement is met, but the aspect ratio of the electrode layer becomes extremely high making it difficult to form
Solution Approach 1:
The patent transitions from a planar electrode layout to a three-dimensional stacked capacitor structure. By stacking multiple capacitor units vertically, the electrode area is effectively increased without requiring excessively high aspect ratios in a single electrode layer, thus resolving the contradiction between capacitance requirements and manufacturability.
Solution Approach 2:
The capacitor structure is divided into multiple stacked units, each with its own electrode layers and dielectric layers. This segmentation allows the total capacitance to be achieved through parallel combination of multiple smaller capacitors, reducing the aspect ratio burden on individual electrode layers.
2Quantity of substance
If the height of the capacitor structure increases, then the electrode area increases, but etching damage occurs and manufacturing yield decreases
Solution Approach 1:
The patent modifies the etching process parameters by introducing a selective etching approach with multiple etching steps and different etching conditions. This allows precise control over the etching depth and profile, preventing etching damage while achieving the required electrode area through vertical stacking.
Solution Approach 2:
The patent applies preliminary protective measures by forming sacrificial layers and using selective etching masks before the main etching process. These preliminary actions protect critical structures from etching damage while enabling the formation of high-aspect-ratio features needed for increased electrode area.
3Productivity
If the density of memory cells is increased, then the product demand is met, but the area occupied by the capacitor structure becomes smaller relatively
Solution Approach 1:
The patent utilizes the vertical dimension to accommodate capacitor structures, allowing memory cells to be packed more densely in the planar direction. By stacking capacitor units vertically, the horizontal area required for each capacitor is reduced, thereby increasing overall memory cell density while maintaining required capacitance values.
4Productivity
If the capacitor structure is made more compact, then the density increases, but the complexity of the design and process becomes higher
Solution Approach 1:
The patent employs universal process modules that can be repeatedly applied to form multiple stacked capacitor units. The same etching, deposition, and patterning processes are used across different layers, reducing process complexity despite the increased structural density. This modular approach allows compact design without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the etch resistance and manufacturing yield by controlling the etching process, ensuring the structural integrity of the capacitor structure while maintaining the required capacitance and density.
Implementation Method 1
An etching rate of a bottom portion of the first support layer in the second etching process is lower than an etching rate of a top portion of the first support layer in the second etching process
Data Source
AI summary
A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.