DRAM Capacitor Lower Electrode Using Self-Aligned Spacers
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Solution Overview
Problem
The challenge in manufacturing DRAM capacitors is to increase memory capacitance while reducing capacitor dimensions, which is hindered by limitations in lithography resolution and the complexity of the MIM capacitor process, requiring multiple reticles and intricate pattern transfer.
Innovation Solution
A manufacturing method involving a semiconductor substrate with a sacrificial laminate, forming capacitor trenches and lower electrode structures, etching back the laminate to expose upper portions, and using a liner layer to create self-aligned insulating spacers, allowing for reduced reticle requirements and simplified integration of memory cell capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If capacitor dimensions are reduced to increase integration density, then device miniaturization is achieved, but memory capacitance decreases
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional stacked capacitor structures. Multiple capacitor layers are stacked vertically on the semiconductor substrate, utilizing the vertical dimension to increase total capacitance while maintaining a small footprint area. This dimensional change allows the device to achieve both miniaturization and increased memory capacitance.
Solution Approach 2:
The patent implements nested capacitor structures where smaller capacitors are positioned within or between larger structural elements. The stacked capacitor layers are integrated within a compact three-dimensional architecture, allowing multiple capacitive elements to occupy overlapping or nested spatial regions, thereby increasing total capacitance without proportionally increasing device area.
2Quantity of substance
If traditional MIM capacitor manufacturing is used to maintain capacitance, then memory capacitance is preserved, but process complexity increases with multiple reticles
Solution Approach 1:
The patent combines multiple capacitor formation operations into a single integrated process step. By forming all capacitor layers simultaneously through conformal deposition on a three-dimensional structure, the method eliminates the need for multiple separate lithography and deposition cycles that would require multiple reticles, thereby reducing process complexity while maintaining total capacitance.
Solution Approach 2:
The patent performs preliminary structuring by forming the three-dimensional sacrificial structure and lower electrode framework before depositing dielectric and upper electrode layers. This preliminary action establishes the vertical architecture in advance, allowing subsequent conformal deposition to automatically create the stacked capacitor configuration without requiring additional lithography patterning steps.
3Manufacturing precision
If optical lithography is improved to increase resolution, then pattern transfer resolution is enhanced, but the fundamental limitation of optical methods remains
Solution Approach 1:
The patent replaces optical lithography with a self-aligned deposition-based patterning method. Instead of using optical systems to define capacitor patterns, the invention uses conformal atomic layer deposition or chemical vapor deposition to automatically form precise three-dimensional structures. This mechanical/chemical substitution eliminates optical diffraction limits and provides superior dimensional control without requiring further optical resolution improvements.
Solution Approach 2:
The patent employs self-aligned formation of capacitor structures where the deposition process automatically conforms to the underlying three-dimensional template. The conformal deposition method uses the existing lower electrode and sacrificial structure as a self-defined mask and template, eliminating the need for external lithography alignment and achieving precise pattern transfer without optical intervention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the miniaturization of DRAM devices with increased yield rates by reducing reticle needs and forming well-defined self-aligned openings, facilitating easier integration of memory cell capacitors.
Implementation Method 1
performing a wet-etching process to remove the sacrificial laminate through the self-aligned openings
Data Source
AI summary
A manufacturing method of capacitor lower electrode of the instant disclosure comprises the steps of: providing a semiconductor substrate; forming a sacrificial laminate on the semiconductor substrate; forming a plurality of capacitor trenches in the sacrificial laminate; forming a plurality of lower electrode structures in the capacitor trenches respectively; etching back the sacrificial laminate to a desired thickness to expose an upper portion of each of the lower electrode structures; forming a liner layer to conformally cover the sacrificial laminate and the upper portions of the lower electrode structures; patterning the liner layer to form an insulating spacer on the sidewalls of each of the upper portions, wherein two adjacent insulating spacers are configured to have a self-aligned opening positioned therebetween; and performing a wet-etching process to remove the sacrificial laminate through the self-aligned openings.