DRAM Capacitor Contact Plug Formation via Interlaced Etching
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Solution Overview
Problem
Conventional methods for preparing dynamic random access memory (DRAM) structures require the double exposure technique and advanced lithographic techniques, such as liquid immersion lithography, to precisely define the size and position of capacitor contact plugs, which are challenging due to the small critical dimension (F) in the nanometer generation.
Innovation Solution
A method involving a series of etching and implanting processes to form conductive plugs extending to opposite sides of an active area, using wet and dry etching techniques with specific etchants and dopants, reduces the precision demands on advanced lithographic techniques by forming interlaced blocks and openings that allow conductive plugs to extend to opposite sides of the active area, thereby postponing the need for double exposure and advanced lithography to the next generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If advanced lithographic techniques such as liquid immersion lithography are used to precisely define the size and position of capacitor contact plugs, then manufacturing precision is improved, but device complexity and process difficulty increase
Solution Approach 1:
The capacitor contact plug formation is divided into multiple stages: first forming line-shaped patterns, then using wet etching to create interlaced first and second blocks, followed by dry etching to form openings. This segmentation allows each step to be performed with standard lithography rather than requiring advanced techniques for the entire process
Solution Approach 2:
The method performs preliminary patterning to form line-shaped patterns and interlaced blocks before forming the final capacitor contact plugs. This preliminary action creates a structured framework that guides subsequent etching processes, enabling precise plug formation without requiring advanced lithography at the final step
2Manufacturing precision
If the double exposure technique is used to pattern electrically isolated tilt active areas, then manufacturing precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
Instead of using double exposure to directly pattern the capacitor contact plugs, the method inverts the approach by first forming line-shaped patterns and then using wet etching to create the interlaced block structure. This inversion simplifies the lithographic requirements while maintaining patterning precision
Solution Approach 2:
The line-shaped patterns and interlaced blocks serve as intermediary structures that mediate between the lithography step and the final capacitor contact plug formation. These intermediaries enable precise plug definition through etching rather than direct lithography, improving ease of manufacture
3Quantity of substance
If the critical dimension is reduced to F in the nanometer generation, then storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The method replaces the mechanical/optical limitation of lithography with chemical etching processes. Wet etching using buffered oxide etchant and dry etching are used to define the interlaced blocks and openings, substituting the need for high-precision lithography with controllable chemical processes that can achieve the required F dimension precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the precision requirements for advanced lithographic techniques, allowing for the extension of conductive plugs to opposite sides of the active area, thereby postponing the need for double exposure and advanced lithography, enhancing the process window for patterning and reducing the complexity of capacitor contact plug formation.
Implementation Method 1
A wet etching process is performed to remove a portion of the line-shaped pattern to decrease the width of the line-shaped patterns
Implementation Method 2
a dry etching process is performed to remove a portion of the dielectric structure not covered by the second etching mask to form a plurality of openings
Implementation Method 3
a first tilt implanting process is performed to implant dopants into the silicon-containing layer outside the predetermined region to change the chemical property of a predetermined portion of the silicon-containing layer
Data Source
AI summary
A method for preparing a memory structure comprises the steps of forming a plurality of line-shaped blocks on a dielectric structure of a substrate, and forming a first etching mask exposing a sidewall of the line-shaped blocks. A portion of the line-shaped blocks is removed incorporating the first etching mask to reduce the width of the line-shaped blocks to form a second etching mask including a plurality of first blocks and second blocks arranged in an interlaced manner. Subsequently, a portion of the dielectric structure not covered by the second etching mask is removed to form a plurality of openings in the dielectric structure, and a conductive plug is formed in each of the openings. The plurality of openings includes first openings positioned between the first blocks and second openings positioned between the second blocks, and the first opening and the second opening extend to opposite sides of an active area.