DRAM Capacitor Spacer Mitigates Leakage in Deep Trenches
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Solution Overview
Problem
The high aspect ratio of deep trench capacitors in DRAM cells leads to leakage issues due to narrow corners and sub-trenches, which can alter data states and require high refresh rates, consuming time and power, and compromising memory performance.
Innovation Solution
A spacer is deposited and selectively etched to modify the sub-trenches and acute corners into obtuse angles, preventing the metal-insulator-metal film from cramming and ensuring smooth deposition, thereby reducing leakage and maintaining capacitance stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the deep trench is made smaller to conserve space on the substrate, then the area occupied by the capacitor is reduced, but the perimeter of the deep trench is significantly reduced, leading to reduced electrical charge capability
Solution Approach 1:
The invention transitions from a planar capacitor design to a three-dimensional stacked capacitor structure. By stacking multiple capacitor layers vertically, the electrical charge capability is significantly increased without occupying additional substrate area. This vertical stacking approach allows multiple capacitors to share the same footprint, effectively resolving the contradiction between minimizing area and maximizing charge storage capacity.
Solution Approach 2:
The stacked capacitor structure employs a nested configuration where multiple capacitor layers are arranged vertically one above another. Each capacitor layer is nested within the same horizontal footprint, with upper layers positioned over lower layers. This nesting arrangement maximizes the use of vertical space to increase total capacitance while maintaining a compact footprint on the substrate.
2Area of stationary object
If the deep trench is made smaller to conserve space, then the area is reduced, but the manufacturing precision becomes more difficult to maintain due to high aspect ratio
Solution Approach 1:
By moving to a stacked capacitor architecture, the invention avoids the need for extremely narrow and deep single trenches. Instead, multiple shallower trenches are stacked vertically, each with more manageable aspect ratios. This dimensional transition makes the manufacturing process more controllable and maintains better trench profile precision throughout fabrication.
3Reliability
If high refresh rates are used to compensate for leakage, then data corruption is prevented, but time and power consumption increase, compromising memory performance
Solution Approach 1:
The invention addresses the leakage issue by transforming the capacitor structure itself rather than compensating through higher refresh rates. The stacked capacitor design with optimized trench profiles and interface structures inherently reduces leakage paths, converting the potential harm of leakage into a benefit of improved charge retention without increasing power consumption or refresh frequency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modified deep trench profile with a spacer minimizes capacitor leakage, stabilizes capacitance, and prevents data corruption, enhancing the reliability and performance of DRAM cells without altering existing dimensions.
Implementation Method 1
A spacer is deposited and selectively etched to modify the sub-trenches and acute corners into obtuse angles
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a source/drain region in a substrate. An interlevel dielectric layer is formed on the substrate. A conducting plug is formed in the interlevel dielectric layer. The conducting plug is electrically coupled to the source/drain region. A crown oxide is formed on the interlevel dielectric layer. A deep trench is formed in the crown oxide to expose a top wall and a sidewall of the conducting plug. A spacer is formed on the sidewall of the conducting plug. A metal-insulator-metal film is formed in the deep trench.