DRAM Command Cancel Function for Error Correction
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Solution Overview
Problem
Existing memory systems face delays in read operations and increased write latency due to non-zero latencies, and memory failures are often caused by issues with command and address signals that are not covered by error correction codes, leading to system outages and reliability concerns.
Innovation Solution
Implementing error correction across all memory command and address signals using the 'Command Cancel' function, which allows for parallel operation with normal memory re-drive methods to correct single or multiple bit failures and prevent system outages, while minimizing latency by canceling invalid operations and enabling rapid recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) is added to memory command and address signals, then reliability is improved, but access time increases due to additional latency
Solution Approach 1:
The patent implements preliminary error detection by monitoring command and address signals before they are executed by the memory device. The controller detects errors in advance using parity checks or ECC on the command/address bus, allowing the system to cancel erroneous commands before they reach the memory device, thus avoiding the need to complete full error correction cycles for every access.
Solution Approach 2:
The patent extracts the error correction function from the main memory access path by implementing separate error detection and cancellation mechanisms. Instead of requiring full ECC processing for every memory operation, the system uses dedicated error detection circuitry that operates in parallel, separating the reliability function from the critical data access path.
2Loss of time
If command cancel function is implemented, then latency is reduced by canceling invalid operations, but device complexity increases
Solution Approach 1:
The patent introduces a command cancel signal as an intermediary mechanism between the controller and memory device. This single-bit signal acts as a mediator that can quickly terminate erroneous commands without requiring complex rollback procedures or multiple status signals, simplifying the overall control logic while enabling rapid cancellation of invalid operations.
Solution Approach 2:
The command cancel function operates periodically at defined intervals in the memory command sequence, allowing the controller to issue cancellation signals at predetermined points in the command timeline. This periodic structure simplifies timing logic and makes the cancel function predictable and easy to implement within the existing memory controller architecture.
Data Source
AI summary
A method for performing a common cancel (CC) function on a dynamic random access memory (DRAM) semiconductor device to improve reliability and speed of a memory system. The CC function rakes advantage of the intrinsic delays associated wit memory read operations at high clock frequencies, and the increased write latency commensurate with increased read latencies where non-zero larencies for read and write operations are the norm by permitting address and command ECC structures to operate in parallel with the address and command re-drive circuitt The CC function is extendable to future DDR2 and DDR3 operating requirements in which latency of higher frequency modes will increase due to the shift from 2 bit pre-fetch to 4 and 8 bit pre-fetch architecture.