DRAM Control Circuit Timing High Current Operations

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Solution Overview

Problem

In semiconductor devices with volatile memory, high current consumption operations like refresh, ZQ calibration, and DLL delay updates generate noise, potentially causing errors when performed simultaneously, leading to mutual interference between operations.

Innovation Solution

A control circuit that triggers a first operation upon a specific signal and switches to a second operation, such as DLL delay value updating or ZQ calibration, after a predetermined number of first operations are performed, allowing these high current operations to be performed at different timings and minimizing mutual effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple high current consumption operations (refresh, ZQ calibration, DLL update) are performed simultaneously to improve productivity, then the total operation throughput increases, but noise increases causing errors and mutual interference between operations

Engineering Contradiction:
Improveoperation throughputVSAvoidoperation accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments high current consumption operations into separate time slots within the refresh cycle. Instead of performing refresh, ZQ calibration, and DLL update simultaneously, the control circuit executes them sequentially: refresh operation first, then ZQ calibration, then DLL update. This temporal segmentation eliminates mutual interference while maintaining all necessary operations, resolving the contradiction between productivity and reliability.

Inventive Principle:
Principle #1Segmentation

2Loss of time

If high current consumption operations are performed simultaneously to reduce loss of time, then the total execution time decreases, but noise-generated errors increase

Engineering Contradiction:
Improveoperation execution timeVSAvoidnoise interference
Core Design Contradiction:
Loss of timeVSObject-affected harmful factors

Solution Approach 1:

The patent implements periodic action by structuring operations in a sequential cycle: refresh operation → ZQ calibration → DLL update. Each operation occurs at a specific periodic interval within the refresh cycle, ensuring that high current operations are separated by time rather than occurring simultaneously. This periodic scheduling minimizes noise interference while maintaining efficient operation timing, addressing the contradiction between execution time and noise reduction.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9082505B2Method for triggering a delay-locked loop (DLL) update operation or an impedance calibration operation in a dynamic random access memory device
Publication Date: 2015.07.14 LONGITUDE LICENSING LTD
  • US9082505B2 patent drawing
  • US9082505B2 patent drawing
  • US9082505B2 patent drawing

AI summary

A method for triggering an adjustment operation in a dynamic random access memory device, the method including receiving a refresh command, generating an execute signal, counting the execute signal to provide a count value, refreshing a memory array based on the count value and triggering the adjustment operation when the count value reaches a predetermined value.