DRAM Controller Address Space Allocation for Mixed Capacities
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Solution Overview
Problem
Conventional memory systems face challenges in efficiently managing and allocating address spaces for dynamic random access memories (DRAMs) of varying capacities, leading to inefficiencies in resource utilization and increased costs due to the need for excessive DRAM installation when capacity is insufficient.
Innovation Solution
A memory system configuration that includes multiple DRAMs with different capacities, where a DRAM controller allocates address spaces of varying bit widths (32-bit, 16-bit, and 8-bit) to each DRAM, allowing for flexible selection based on input addresses and threshold addresses, enabling efficient access and reducing the need for excessive DRAM installation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAMs of varying capacities are installed to match different address space requirements, then resource utilization efficiency is improved, but device complexity increases due to managing multiple DRAM types
Solution Approach 1:
The system changes the parameter of address space bit width (32-bit, 16-bit, 8-bit) to match different DRAM capacities. The controller allocates different address space configurations to different DRAMs based on their capacities, allowing efficient utilization of each DRAM's storage space without waste.
Solution Approach 2:
The system segments the address space into different bit width portions (32-bit, 16-bit, 8-bit) and assigns each segment to appropriate DRAMs based on capacity. This segmentation allows the controller to manage multiple DRAM types by treating each capacity group with its corresponding address space configuration.
2Reliability
If excessive DRAM is installed to ensure sufficient capacity, then capacity shortage is eliminated, but cost increases due to unused memory resources
Solution Approach 1:
The system uses different address space bit widths (32-bit, 16-bit, 8-bit) as parameters to precisely match DRAM capacities. This allows the system to allocate exactly the right amount of address space to each DRAM, eliminating both capacity shortages and the waste of excessive installation.
Solution Approach 2:
The controller dynamically selects which DRAM to access based on the input address and the allocated address space ranges. This dynamic allocation allows the system to efficiently utilize available DRAM capacities without requiring over-provisioning for future needs.
3Device complexity
If a unified address space allocation method is used for all DRAMs, then device complexity is reduced, but resource utilization efficiency deteriorates due to inability to optimize for different capacities
Solution Approach 1:
The system applies different address space parameters (32-bit, 16-bit, 8-bit) to different DRAMs based on their capacities. The controller includes logic to determine which address space configuration to use based on the DRAM being accessed, optimizing resource utilization while maintaining manageable complexity through systematic parameter assignment.
Data Source
AI summary
A memory system includes a first volatile memory having an access unit of a first bit width; a second volatile memory having an access unit of the first bit width and having a capacity larger than the first volatile memory; and a controller connected to the first and second volatile memories. The controller allocates a first address space having the first bit width as a unit to the first volatile memory, allocates a second address space having the first bit width as a unit to the second volatile memory, selects at least one of the first and second volatile memories based on a first address indicating a position in a third address space having a second bit width as a unit, calculates a second address in the address space allocated to the selected volatile memory, and accesses a position corresponding to the second address of the selected volatile memory.