DRAM Cross-Fail Detection Using Redundant Bit Line Inversion
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Solution Overview
Problem
Conventional methods for testing dynamic random access memory (DRAM) devices are ineffective in identifying and compensating cross-fail issues, as they can lead to additional memory cells connected to the same bit line becoming defective due to capacitive connections caused by process errors, especially under high temperature and voltage stresses.
Innovation Solution
A method involving a multi-word line test mode with the addition of a high frequency disturbing signal to identify cross-fail by measuring signal changes on bit lines, allowing for the effective use of a redundant bit line memory array to replace defective cells, thereby isolating the failure and preventing further damage to connected memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a redundant word line memory array is used to replace a defected memory cell, then the defected cell can be compensated, but other memory cells connected to the same bit line may become defective due to capacitive connection
Solution Approach 1:
Instead of replacing the defective memory cell with a redundant word line (conventional approach), the patent inverts the replacement strategy by using a redundant bit line to replace the defective cell. This inversion resolves the capacitive connection issue because the gate electrode is connected to the original word line, not the redundant bit line, thereby preventing additional failures in other memory cells on the same bit line
Solution Approach 2:
The patent extracts the problematic capacitive connection from the system by identifying and isolating the specific memory cell with the cross-fail defect. By replacing only this specific cell with a redundant bit line configuration, the harmful capacitive connection is removed while preserving the functionality of other memory cells connected to the same bit line
2Ease of operation
If conventional testing methods are used, then the testing process is simple, but cross-fail issues cannot be identified
Solution Approach 1:
The patent applies preliminary action by performing a specific testing sequence before final product determination. The method first applies a first voltage to the word line, then applies a second voltage to the bit line, and measures the current. This preliminary testing action enables detection of cross-fail defects that would be missed by conventional single-voltage testing methods
Solution Approach 2:
The patent introduces an intermediary measurement approach by using current measurement as an intermediate step to detect cross-fail defects. Instead of directly observing the capacitive connection, the method uses the intermediary effect of current flow when both voltages are applied, which reveals the presence of cross-fail defects through abnormal current readings
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate identification and compensation of cross-fail in DRAM devices by using a redundant bit line memory array, ensuring that only the affected memory cells are replaced, thereby maintaining the integrity of the memory array without affecting other cells connected to the same bit line.
Implementation Method 1
The protrusion 305 may cause a capacitive connection between the gate electrode 310 and the bit line 340
Implementation Method 2
adding a disturbing signal on the actuated word line and measuring signals on the plurality of bit lines
Data Source
AI summary
A method for testing a semiconductor memory device is provided. The semiconductor memory device includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Each word line is controlled by a corresponding control line and a corresponding driving line. The method includes selecting a plurality of word lines controlled by one driving line; enabling a plurality of control lines respectively corresponding to the selected word lines; actuating one of the selected word lines; and adding a disturbing signal on the actuated word line and measuring signals on the plurality of bit lines.