DRAM Controller Early Notification for Frequency Switch
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Solution Overview
Problem
Current DRAM clock frequency change techniques are inefficient, leading to system performance degradation in real-time applications due to prolonged suspension of memory operations during frequency changes, which is undesirable in power-conscious environments like mobile computing.
Innovation Solution
A DRAM controller system that issues an early notification signal to gradually decrease queue occupancy to a target level before switching the clock frequency, allowing for faster frequency changes while maintaining timing constraints, thereby reducing the time interval between requesting and completing the clock frequency change.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clock frequency change is implemented to save power in mobile computing systems, then power consumption is reduced, but system performance degrades due to prolonged suspension of memory operations
Solution Approach 1:
The patent applies preliminary action by having the processing circuit issue an early notification signal before the actual clock frequency switch signal. This allows the DRAM controller to prepare for the frequency change in advance by decreasing queue occupancy to a target level, so that when the frequency switch occurs, memory operations can resume quickly without prolonged suspension, thus reducing the impact on system performance while still achieving power savings.
2Productivity
If queue occupancy is not decreased before clock frequency change, then memory operations can continue without interruption, but the time interval for frequency change increases causing performance degradation
Solution Approach 1:
The DRAM controller decreases queue occupancy to a target level in advance upon receiving the early notification signal, before the actual frequency switch occurs. This preliminary preparation ensures that when the clock frequency changes, the queue is already in an optimal state for quick resumption of memory operations, minimizing the time interval and maintaining operation continuity.
Solution Approach 2:
The system uses feedback through the early notification signal mechanism. The processing circuit notifies the DRAM controller of the upcoming frequency change, allowing the controller to adjust queue occupancy accordingly. This feedback loop enables coordinated action between the processing circuit and DRAM controller to optimize both frequency change speed and operation continuity.
3Reliability
If complex queue management is implemented to maintain timing constraints during frequency change, then system reliability is improved, but device complexity increases
Solution Approach 1:
The DRAM controller simply decreases queue occupancy to a predetermined target level in advance, rather than implementing complex dynamic queue management during the frequency change. This preliminary action to a fixed target level simplifies the controller design while still ensuring timing constraints are satisfied, as the queue is prepared in advance rather than managed dynamically during the transition.
Data Source
AI summary
A computing system for accessing a dynamic random access memory (DRAM) includes a processing circuit, a queue, and a DRAM controller. The processing circuit is configured for issuing an early notification signal before issuing a clock frequency switch signal; the early notification signal notifies upcoming of the clock frequency switch signal and the clock frequency switch signal requests a change of frequency of a DRAM clock. The queue has N entries and each entry stores at least an address and an associated command to be sent to the DRAM. The DRAM controller is configured for controlling access to the DRAM and the DRAM controller manages to decrease occupancy of the queue to a target level upon receiving the early notification signal.