DRAM Decoder Masks MRW Commands on Shared CA Bus
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Solution Overview
Problem
Current DRAM memory configurations that share a common command address (CA) bus cannot be individually configured using mode register write (MRW) commands, leading to less than optimal settings for each memory device.
Innovation Solution
Implementing a decoder in each DRAM device that determines whether to mask MRW commands received over the shared CA bus, allowing individual configuration of each device by ignoring or executing configuration information based on the decision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple DRAM devices share a common command address (CA) bus, then device complexity and resource utilization are improved, but individual configuration capability deteriorates
Solution Approach 1:
The patent segments the configuration process by introducing per-device decoders that can independently mask MRW commands. Each DRAM device's decoder evaluates device-specific criteria (such as device type, capacity, or initialization state) to determine whether to mask configuration commands, enabling individualized configuration paths while sharing the common CA bus.
Solution Approach 2:
The patent introduces decoder logic as an intermediary component between the common CA bus and each DRAM device's configuration register. This intermediary selectively blocks or passes MRW commands based on device-specific conditions, allowing the system to maintain a simple shared bus architecture while achieving complex individualized configuration capabilities.
2Ease of operation
If all DRAM devices on a shared CA bus receive the same MRW commands, then bus operation simplicity is improved, but configuration optimization deteriorates
Solution Approach 1:
The patent applies local quality by making each DRAM device's response to MRW commands device-specific. Each device's decoder evaluates local device characteristics and applies masking independently, so that while the bus operation remains simple and uniform, each device receives effectively customized configuration commands appropriate to its specific requirements.
3Manufacturing precision
If MRW commands are masked for individual devices, then configuration precision is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling each DRAM device to autonomously evaluate its own configuration needs through local decoder logic. Each device independently determines whether to mask MRW commands based on its own characteristics and state, eliminating the need for complex external control logic while achieving precise individualized configuration.
Data Source
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AI summary
Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.