DRAM On-Die ECC Check Bit Extraction for System-Level Reliability
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Solution Overview
Problem
Current memory systems face challenges in effectively managing and accessing error correction data from memory devices, as on-die error checking and correction (ECC) logic within DRAMs does not provide insight to system-level ECC, potentially exposing sensitive information about the memory design and operation.
Innovation Solution
A memory subsystem that generates internal check bits after performing error detection and correction, allowing selective exposure of ECC information to the memory controller, which can use these bits for system-level ECC without revealing single bit error details, thereby maintaining privacy while improving error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die ECC logic provides full error correction details to system level, then system-level ECC reliability is improved, but sensitive information about memory design and operation is exposed
Solution Approach 1:
The patent extracts only the essential error correction status information (correctable vs. uncorrectable error states) from the detailed on-die ECC data, transmitting only this condensed information to system level. This allows system-level ECC to function reliably without exposing sensitive details about specific bit patterns or memory locations that would reveal design information.
Solution Approach 2:
The patent applies different information disclosure policies to different error states: full error correction capability is provided for multibit uncorrectable errors (where system-level intervention is needed), while single-bit correctable errors maintain privacy (where on-die correction suffices). This local differentiation resolves the contradiction by providing information only where necessary for reliability while protecting sensitive data elsewhere.
2Loss of information
If on-die ECC logic withholds all error correction information, then sensitive information is protected, but system-level ECC cannot effectively manage errors
Solution Approach 1:
The patent implements partial information disclosure by providing just enough error status information (error state categories) for system-level ECC to function effectively, without providing excessive detailed information about specific error locations or patterns. This partial action satisfies system-level needs while maintaining security.
Solution Approach 2:
The patent segments error information into distinct categories (no error, single-bit correctable error, multibit uncorrectable error) and transmits only the segmented category information to system level. This segmentation allows system-level ECC to manage different error types appropriately while preventing reconstruction of sensitive detailed error information.
3Ease of operation
If detailed error correction data is transmitted to memory controller, then error management capability is improved, but data privacy and security are compromised
Solution Approach 1:
The patent extracts only the essential operational information needed for error management (error state categories indicating what type of correction is needed) from the complete error correction dataset. This extracted information enables effective error management while the omitted details preserve data privacy and security.
4Loss of information
If minimal error correction information is provided to system level, then data privacy is maintained, but system-level ECC reliability deteriorates
Solution Approach 1:
The patent applies differentiated information provision: minimal information (error state categories) is provided for privacy-sensitive single-bit errors, while more information is provided for multibit uncorrectable errors where system-level intervention is critical for reliability. This local quality approach maintains privacy where possible while ensuring reliability where necessary.
Data Source
AI summary
Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.