DRAM Frequency Reset via Self-Refresh Entry Sequence
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Solution Overview
Problem
In DRAM systems, frequency mismatches between System-on-Chip (SoC) and Dynamic Random Access Memory (DRAM) during reset events lead to unreliable communication, causing loss of crash logs and hindering debugging, as current standards like JEDEC JESD209-4 LPDDR4 do not provide a solution for this issue.
Innovation Solution
Implementing a special Self-Refresh (SR) entry sequence and a new Mode Register (MR) write command to reset the Frequency Set Points (FSP) of DRAM to FSP0, ensuring synchronized FSP states between SoC and DRAM, thereby preventing communication failures and allowing safe retrieval of crash logs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the SoC defaults to FSP0 at power-up while DRAM may be at FSP0 or FSP1 after a crash, then the SoC can initialize quickly, but frequency mismatch occurs causing unreliable communication and loss of crash logs
Solution Approach 1:
The patent applies preliminary action by having the SoC issue a self-refresh command to DRAM before attempting to read crash logs. This preliminary action ensures that DRAM is in a known state (FSP0) before communication begins, preventing frequency mismatch issues while maintaining quick initialization.
Solution Approach 2:
The patent implements feedback by monitoring the state of DRAM and adjusting the initialization sequence accordingly. The SoC checks whether DRAM is in self-refresh mode and adapts its communication strategy, ensuring reliable communication regardless of the initial DRAM frequency state.
2Reliability
If the SoC issues a mode register write command to reset FSP during self-refresh, then frequency synchronization is attempted, but the command is ignored causing FSP mismatch to persist
Solution Approach 1:
The patent applies preliminary action by issuing the self-refresh command before the mode register write command. This sequence ensures that DRAM is in the correct state to accept the FSP reset, preventing the command from being ignored and avoiding the need for complex retry logic.
Solution Approach 2:
The patent implements dynamics by making the initialization sequence adaptive based on DRAM's response. If the mode register write command is initially ignored, the system dynamically adjusts by waiting for DRAM to exit self-refresh and then re-issuing the command, ensuring frequency synchronization without excessive complexity.
3Loss of information
If the system flushes crash logs to DRAM before reset, then crash logs are preserved, but DRAM must be brought out of self-refresh causing communication failures due to FSP mismatch
Solution Approach 1:
The patent applies preliminary action by ensuring DRAM is in the correct frequency state (FSP0) before attempting to flush crash logs. The self-refresh command is issued beforehand to synchronize frequencies, ensuring that the log flush operation can proceed without communication failures.
Solution Approach 2:
The patent implements preliminary anti-action by preventing the frequency mismatch problem before it occurs. By forcing DRAM into self-refresh mode before the log flush, the system preemptively eliminates the condition that would cause communication failure, allowing safe retrieval of crash logs.
Data Source
AI summary
Some aspects of the disclosure include a self-refresh entry sequence for a memory, such as a DRAM, that may be used to avoid a frequency mismatch between a system processor and a system memory. The self-refresh entry sequence may signal the memory to reset the frequency set point state and default to the power-up state upon a self-refresh process exit. In another aspect, a new mode register may be used to indicate that the frequency set point needs to be reset after the next self-refresh entry command. In this aspect, the processor will execute a mode register write command followed by a self-refresh entry in response to the occurrence of a crash event. Then, the memory will reset to the default frequency set point by the end of self-refresh entry execution.