DRAM Memory Interleaving for Rank Access Efficiency
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Solution Overview
Problem
In memory systems with multiple ranks, accessing data from different memory pages leads to inefficiency due to pre-charging and latency, resulting in idle data bus cycles and reduced throughput, especially when consecutive data is stored in the same memory rank.
Innovation Solution
A memory interleaving method where continuous data with continuous logical addresses is distributed across multiple memory ranks, using specific bits as an interleaving control code to determine the memory rank allocation, allowing for efficient data access by decoding the logical address to obtain the physical location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in the same memory rank for sequential access, then memory space utilization is improved, but access efficiency deteriorates due to pre-charging and latency
Solution Approach 1:
The patent segments the memory system into multiple independent memory ranks, each capable of autonomous operation. By dividing the memory address space across multiple ranks and enabling independent activation of each rank, the system can access data from different ranks simultaneously without requiring pre-charging operations, thus resolving the contradiction between memory space utilization and access efficiency
Solution Approach 2:
The patent introduces a new dimension of parallelism by utilizing multiple memory ranks that can operate independently and simultaneously. This dimensional expansion allows the system to perform multiple memory operations in parallel across different ranks, eliminating the sequential pre-charging latency that plagues single-rank systems and thereby improving both space utilization and access efficiency
2Ease of operation
If memory page is activated before reading operation, then data access is enabled, but time is spent on activation and latency
Solution Approach 1:
The patent performs preliminary actions by pre-fetching data from multiple memory ranks into buffer memory before the actual read operation is needed. The controller anticipates future data access requirements and proactively loads data into the buffer, so when data is actually requested, it is already available in the buffer, eliminating activation and latency delays
Solution Approach 2:
The patent introduces a buffer memory as an intermediary between the memory ranks and the data bus. This buffer acts as a mediator that decouples the timing between memory activation and data access, allowing data to be transferred to the buffer during latency periods and then quickly delivered to the data bus when needed, thereby reducing the perceived activation and latency time
3Reliability
If data bus is idle during activation and latency periods, then memory operations are completed, but system throughput is reduced
Solution Approach 1:
The patent ensures continuity of useful action by maintaining constant data flow through the system. While memory operations are completing in the background, the buffer memory continuously supplies data to the data bus, ensuring that the data bus remains active and productive throughout the entire operation cycle, thereby eliminating idle periods and maximizing system throughput while maintaining reliable memory operation completion
Data Source
AI summary
A method is disclosed for utilizing at least one bit within the logical address code of a memory unit formed by Dynamic Random Access Memory (DRAM) to be the control code for interleaving the memory space to different memory ranks. First, the distributive rule of the data is defined. Next, the data is distributed to the memory ranks that the data belongs to according to the rule. Then, the data is physically accessed in one of the memory ranks.