DRAM Latency Control Circuit for Clock Domain Crossing
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face limitations in increasing the frequency of the main clock signal, which restricts the operation speed of the core circuit, leading to potential data loss due to domain crossing between the main clock and data clock signals, necessitating improved latency control for stable data input/output operations.
Innovation Solution
A memory device incorporating a latency control circuit that generates and adjusts latency information based on phase synchronization between the main clock and data clock signals, using dividers to create aligned and synchronized clock signals, ensuring accurate data transfer across different clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the main clock signal is increased to improve operation speed, then the productivity of the core circuit is improved, but the reliability of data transfer deteriorates due to domain crossing between main clock and data clock signals
Solution Approach 1:
The patent introduces a latency control circuit as an intermediary component that mediates between the main clock domain and data clock domain. This circuit generates latency information based on phase detection between divided versions of the two clock signals, and uses this information to adjust the timing of control signals. By inserting this intermediary latency adjustment mechanism, the system can maintain high main clock frequencies while ensuring reliable data transfer across clock domains, as the latency control circuit compensates for phase misalignment that would otherwise cause data loss.
2Speed
If the main clock frequency is increased to improve processing speed, then the speed of the core circuit is improved, but the loss of information increases due to domain crossing issues
Solution Approach 1:
The patent implements a feedback mechanism where the latency control circuit continuously monitors the phase relationship between divided main clock signals and divided data clock signals. The phase detection output feeds back to adjust the latency control settings, which in turn modifies the timing of control signals to prevent data loss. This closed-loop feedback system enables the core circuit to operate at high speeds while dynamically compensating for domain crossing issues that would otherwise cause information loss.
Data Source
AI summary
A memory device is provided. The memory device receives a main clock signal and provides an internal main clock signal; a data clock buffer to receive a data clock signal; and a latency control circuit configured to generate latency information based on the data clock signal and provide the latency information to a data circuit. The latency control circuit includes: a divider configured to generate divided-by-two clock signals based on the data clock signal; a divider configured to generate divided-by-four clock signals based on a first group of the divided-by-two clock signals; a first synchronization detector configured to output divided-by-two alignment signals indicating whether a second group of divided-by-two clock signals is synchronized with the data clock signal; and a latency selector configured to detect phases of the divided-by-four clock signals based on the divided-by-two alignment signals and adjust a latency of the main clock signal based on the phases.