DRAM Source/Drain Junction Leakage Mitigation via Self-Aligned Doping

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Solution Overview

Problem

In semiconductor devices, misalignment during the formation of contact pads can lead to recesses in the diffused regions, causing leakage current across p-n junctions and reducing data retention time in memory cells.

Innovation Solution

The introduction of an additional doped region, self-aligned with the contact pads, connects divided source/drain regions, preventing leakage current by ensuring a suitable reverse bias voltage can be applied across the p-n junction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a self-alignment process is used to form contact pads with larger top surfaces, then alignment margin during contact hole formation is improved, but misalignment of mask pattern may cause recesses in diffused regions leading to leakage current

Engineering Contradiction:
Improvealignment marginVSAvoidleakage current
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming an additional doped region in advance, self-aligned with the contact pad, before the potential misalignment problem occurs during mask patterning. This additional doped region is created through a preliminary doping step that compensates for future alignment issues, ensuring the diffused region remains continuous even if recesses form during subsequent processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies local quality by creating a specific additional doped region localized at the contact pad area, rather than uniformly doping the entire substrate. This localized doping approach addresses the specific problem area where misalignment might occur, maintaining the continuity of the diffused region precisely where needed without affecting other areas of the device.

Inventive Principle:
Principle #3Local quality

2Productivity

If the pitch of gate electrodes is reduced to decrease memory cell size, then device density is improved, but the area of diffused region exposed from gate electrodes is reduced making alignment more difficult

Engineering Contradiction:
Improvedevice densityVSAvoidalignment precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent introduces an intermediary element - the additional doped region - that acts as a mediator between the contact pad and the main diffused region. This intermediary doped region ensures continuous electrical connection even when the exposed area of the diffused region is reduced due to smaller pitch, effectively bridging the alignment gap that arises from high-density packaging requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The additional doped region is formed in advance during the doping process, before the alignment challenges of high-density patterning become critical. This preliminary formation of the additional doped region ensures that even when subsequent steps face alignment difficulties due to reduced pitch, the electrical continuity is already established.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively reduces leakage current across the p-n junction, improving the data retention time of memory cells by about 20% compared to conventional techniques.

Implementation Method 1

introducing impurities into a portion of the source/drain regions by a self-alignment process using the contact pads as a mask

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS7618869B2Manufacturing method for increasing product yield of memory devices suffering from source/drain junction leakage
Publication Date: 2009.11.17 HEFEI RELIANCE MEMORY LTD
  • US7618869B2 patent drawing
  • US7618869B2 patent drawing
  • US7618869B2 patent drawing

AI summary

A DRAM device includes contact pads having a bottom in contact with a corresponding source/drain region 21 and a top in contact with a bottom of an overlying contact plug. The source/drain region has a recess caused by misalignment of the contact pad with respect to the source/drain region, the recess causing division of the original source/drain region. An additional diffused region is formed by ion-implantation to couple the divided source/drain region to reduce the junction leakage current flowing across the source/drain region.