DRAM Self-Refresh Leakage Control via Voltage Segmentation
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Solution Overview
Problem
Dynamic random access memory (DRAM) experiences internal leakage current issues that persist even when idle, leading to data decay and potential errors due to incomplete voltage recovery during self-refresh mode.
Innovation Solution
A memory device architecture incorporating a switch device to separate and step down the positive power voltage within the memory array, utilizing a controller to manage refresh and pre-startup signals to maintain voltage levels and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the voltage of the positive power VP is lowered before the memory device enters self-refresh mode, then the leakage current is decreased, but the voltage cannot revert back to the original voltage level in waiting time tXSR, causing the memory device to fall into an error
Solution Approach 1:
The patent divides the positive power voltage supply into two separate paths: one for the memory array and one for the decoder. By segmenting the power supply, the memory array can maintain its voltage level while the decoder's voltage is reduced, thereby reducing leakage current without affecting the memory array's operational reliability.
Solution Approach 2:
The patent applies different voltage levels to different parts of the system: the memory array operates at the original positive power voltage level to maintain reliability, while the decoder operates at a reduced voltage level to minimize leakage current. This local differentiation of voltage quality resolves the contradiction between energy loss and operational reliability.
2Reliability
If the voltage of the positive power VP is maintained at the original voltage level, then the memory device can operate accurately, but the leakage current continues to flow from the positive power VP to the negative power VN through the decoder
Solution Approach 1:
The patent segments the power distribution system into separate voltage domains for the memory array and decoder. The memory array receives full positive power voltage to ensure accurate operation, while the decoder receives a reduced voltage to minimize continuous leakage current flow, thus resolving the contradiction between maintaining reliability and reducing energy loss.
Solution Approach 2:
Different voltage qualities are applied locally: the memory array region maintains high voltage for accurate operation, while the decoder region operates at reduced voltage to minimize leakage. This spatial differentiation of voltage quality allows the system to simultaneously achieve both reliability and energy efficiency.
Data Source
AI summary
A memory device includes a memory array, a switch device, and a controller. The switch device is arranged between a first voltage node and a second voltage node. The second voltage node is connected to the memory array. The controller is enabled to output a refresh mode signal, a refresh trigger signal, and a pre-start up signal. The memory device enters a self-refresh mode in response to the refresh mode signal. The memory device performs a self-refresh on the memory array in the self-refresh mode. In self-refresh mode, the controller outputs the pre-start up signal first prior to the refresh trigger signal to enable the switch device, so that the voltage of the second voltage node is increased to the voltage of the first voltage mode.