DRAM Row Merging via Hardware Mapping Table
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) row refreshes consume a significant portion of power, and existing software-based solutions for deduplicating identical data across DRAM rows are computationally expensive and limited in execution, especially when total system memory falls below a threshold.
Innovation Solution
A hardware-based approach for DRAM row merging, where a memory controller identifies rows with identical data and maps them to a reserved row, excluding these rows from refresh operations by using a mapping table and bitmap to indicate which rows should be skipped during refresh, thereby reducing the need for frequent data copying and computational overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If software-based deduplication is used to identify and merge identical DRAM rows, then data redundancy is reduced, but computational overhead increases significantly
Solution Approach 1:
The patent replaces software-based computational deduplication with hardware-based mechanisms including a mapping table and bitmap stored in the memory controller. The hardware automatically tracks row mappings and identifies duplicate rows through bitwise operations on the bitmap, eliminating the need for expensive software computation while maintaining deduplication functionality
Solution Approach 2:
The memory controller performs automatic row merging and tracking without requiring external software intervention. The bitmap and mapping table enable the system to self-identify duplicate rows and self-manage the merging process, reducing computational overhead while achieving energy savings from reduced refresh operations
2Loss of energy
If software-based deduplication solutions are implemented, then identical data rows are merged, but the solutions are limited in execution when total system memory falls below a threshold
Solution Approach 1:
The hardware-based mapping table and bitmap mechanism provides universal functionality that operates independently of system memory conditions. The same hardware structure handles both small and large memory systems without requiring different software implementations, making the solution adaptable across various memory configurations and thresholds
3Reliability
If all DRAM rows are refreshed to ensure data integrity, then data reliability is maintained, but power consumption increases
Solution Approach 1:
The patent extracts and identifies duplicate rows from the set of all DRAM rows using the bitmap and mapping table. By separating identical data into a single representative row and excluding duplicates from refresh operations, the system maintains data integrity for unique data while eliminating unnecessary refresh power consumption for redundant data
Solution Approach 2:
The refresh operation is differentiated by row: unique rows receive full refresh treatment to maintain data integrity, while duplicate rows are excluded from refresh since their data is maintained in the representative row. This local differentiation optimizes power consumption while preserving reliability where needed
4Speed
If multiple identical DRAM rows are maintained, then data accessibility is improved, but the number of refresh operations increases
Solution Approach 1:
The mapping table acts as an intermediary that translates access requests to merged rows into accesses of the representative row. This intermediary structure maintains fast data accessibility by providing direct mapping paths while enabling the system to refresh only the representative row, thereby reducing total refresh operations and power consumption
Data Source
AI summary
Hardware-assisted Dynamic Random Access Memory (DRAM) row merging, including: identifying, by a memory controller, in a DRAM module, a plurality of rows storing identical data; storing, in a mapping table, data mapping one or more rows of the plurality of rows to another row; and excluding the one or more rows from a refresh the DRAM module.