DRAM Error Marking via Correctable Error History Tracking

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Solution Overview

Problem

Dynamic random access memories (DRAMs) experience uncorrectable errors due to bursts of correctable errors and simultaneous errors in different channels, which existing error correction systems fail to address effectively before a memory scrub operation.

Innovation Solution

Implementing a marking system that uses error counters to track correctable errors and sets marks on memory components only when an uncorrectable error occurs, thereby reducing the likelihood of future uncorrectable errors without waiting for a memory scrub.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction relies solely on traditional ECC codes and periodic memory scrubbing, then the system structure remains simple, but uncorrectable errors occur during bursts of correctable errors or simultaneous errors in multiple channels

Engineering Contradiction:
Improveerror correction capabilityVSAvoiderror correction system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by maintaining error indicators that track correctable errors in real-time before they accumulate into uncorrectable bursts. The system proactively identifies memory components experiencing error bursts and marks them for exclusion before uncorrectable errors occur, rather than waiting for periodic scrubbing operations or relying solely on ECC correction capabilities.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces error indicators as intermediary components between the memory components and the error correction system. These indicators act as mediators that monitor error patterns and provide early warning signals, enabling the system to take preventive actions (marking memory components) based on error history rather than reacting only to actual uncorrectable errors.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If memory scrub operations are performed frequently to detect and mark erroneous memory components, then uncorrectable errors are reduced, but system productivity decreases due to increased scrub overhead

Engineering Contradiction:
Improvedata reliabilityVSAvoidsystem throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies self-service by enabling memory components to autonomously track their own error patterns through error indicators. Each memory component's error history is monitored independently, allowing the system to identify problematic components based on their self-reported error patterns rather than requiring external scrubbing operations to detect errors. This reduces the frequency and overhead of scrub operations while maintaining reliable error detection.

Inventive Principle:
Principle #25Self-service

3Reliability

If error indicators are maintained for all memory components to enable proactive marking, then uncorrectable errors are reduced, but the complexity of error tracking and marking logic increases

Engineering Contradiction:
Improveerror prevention capabilityVSAvoiderror tracking complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the error tracking system into independent error indicators for each memory component. Rather than implementing a single complex centralized error tracking system, the patent segments error monitoring into discrete, manageable units (one error indicator per memory component), each tracking its own error patterns independently. This modular approach simplifies the overall system architecture while enabling comprehensive error monitoring.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10296417B2Reducing uncorrectable errors based on a history of correctable errors
Publication Date: 2019.05.21 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10296417B2 patent drawing
  • US10296417B2 patent drawing
  • US10296417B2 patent drawing

AI summary

In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.