DRAM Memory Core Equalizer for Voltage Sensing
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Solution Overview
Problem
The fineness of semiconductor processes and reduction of power voltage make it difficult to write data and sense voltage differences in DRAM memory devices, affecting the performance of semiconductor memory devices.
Innovation Solution
A semiconductor memory device with a memory core that includes first and second memory cells connected to bit-lines and word-lines, an equalizer that transitions voltages between bit-lines, and a control signal generator to manage voltage levels, amplifying voltage differences and providing them to sense amplifiers for stable sensing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor processes are made finer and power voltage is reduced, then device integration and power efficiency are improved, but voltage difference sensing and data writing become more difficult
Solution Approach 1:
The equalizer performs preliminary voltage adjustment on the bit-lines before the read operation. By transitioning bit-line voltages to a predetermined level in advance (when bit-lines are floating), the equalizer prepares the bit-lines to exhibit a larger voltage difference during the subsequent read operation, compensating for the reduced voltage swing caused by finer processes and lower power voltages.
Solution Approach 2:
The equalizer changes the voltage parameter of the bit-lines dynamically. It transitions bit-line voltages from an initial level to a predetermined level during the floating period, and then allows them to transition to a second predetermined level during the read operation. This parameter manipulation enhances the voltage difference for sensing without requiring higher power voltages.
2Use of energy by moving object
If power voltage is reduced, then power efficiency is improved, but data writing and sensing operations become more difficult
Solution Approach 1:
The equalizer performs preliminary voltage adjustment on the bit-lines before the read operation. By transitioning bit-line voltages to a predetermined level in advance (when bit-lines are floating), the equalizer prepares the bit-lines to exhibit a larger voltage difference during the subsequent read operation, compensating for the reduced voltage swing caused by finer processes and lower power voltages.
Solution Approach 2:
The equalizer changes the voltage parameter of the bit-lines dynamically. It transitions bit-line voltages from an initial level to a predetermined level during the floating period, and then allows them to transition to a second predetermined level during the read operation. This parameter manipulation enhances the voltage difference for sensing without requiring higher power voltages.
Data Source
AI summary
A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages.