DRAM Memory Structure Fabrication via Vertical Stacking
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Solution Overview
Problem
The fabrication process of dynamic random access memory (DRAM) is complicated due to the need for increased dimensions of the memory capacitor components, which requires a thicker interlayer dielectric layer, making it unsuitable for front-end-of-line processes and necessitating a multi-layer interconnect structure for electrical connection, complicating the integration with CMOS devices.
Innovation Solution
A method for fabricating DRAM involving the formation of a memory structure with a first conductive layer, a memory medium layer, and a second conductive layer within an opening in the interlayer dielectric layer, allowing for compatibility with CMOS processes and eliminating the need for a multi-layer interconnect structure for electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory capacitor components are increased in dimension to improve storage capacity, then the storage capacity is improved, but the interlayer dielectric layer thickness must be increased, making it unsuitable for front-end-of-line processes and complicating the fabrication process
Solution Approach 1:
The patent transitions from planar capacitor structures to vertically stacked 3D capacitor structures. The memory capacitor is formed with multiple stacked layers (first conductive layer, first dielectric layer, second conductive layer, second dielectric layer) extending in the vertical dimension, thereby increasing storage capacity without requiring larger lateral dimensions that would complicate the interlayer dielectric layer thickness and fabrication process
Solution Approach 2:
The patent embeds the memory capacitor structure within the interlayer dielectric layer during the front-end-of-line CMOS fabrication process. The capacitor components are nested within the existing process flow, with the capacitor forming region created by patterning and etching steps that are integrated into the standard CMOS sequence, eliminating the need for separate post-CMOS capacitor fabrication steps
2Quantity of substance
If a thicker interlayer dielectric layer is used to accommodate larger memory capacitor components, then the storage capacity is improved, but the compatibility with front-end-of-line processes is lost and multi-layer interconnect structures are required
Solution Approach 1:
The patent performs preliminary patterning and preparation steps during the front-end-of-line CMOS process to define the capacitor forming region before the interlayer dielectric layer is fully formed. The capacitor structure is built up concurrently with the interlayer dielectric layer deposition, ensuring that the final capacitor height and interlayer dielectric thickness are coordinated to maintain process compatibility
Solution Approach 2:
The patent designs the memory capacitor structure to serve multiple functions: the stacked conductive and dielectric layers provide both the capacitive storage function and the necessary electrical connections to source and drain regions. The top conductive layer serves as both the capacitor electrode and the connection point to the bit line, eliminating the need for separate multi-layer interconnect structures
Data Source
AI summary
A dynamic random access memory (DRAM) is provided and includes a base substrate. The base substrate includes a semiconductor substrate, a plurality of fins formed on the semiconductor substrate, and an isolation structure formed on the semiconductor substrate and covering portions of side surfaces of the plurality of fins. The dynamic random access memory further includes an interlayer dielectric layer formed over the base substrate and covering top surfaces of the plurality of fins and the isolation structure; and a memory structure, formed in an opening passing through the interlayer dielectric layer and each of the plurality of fins, the opening extending to and exposing a top surface of a portion of the isolation structure. The memory structure includes a first conductive layer, a memory medium layer on the first conductive layer, and a second conductive layer on the memory medium layer.