DRAM Refresh Control Using Partial Array Self-Refresh
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In Dual Data Rate (DDR) memory systems, the increased density of DRAM leads to higher power consumption due to unnecessary refresh operations, as all memory locations are refreshed regardless of usage, wasting energy and increasing command bandwidth.
Innovation Solution
Implementing a partial array self-refresh (PASR) mechanism that allows the memory controller to specify which rows to refresh using explicit ACT and PRE commands, and utilizing a refresh counter to skip rows during auto-refresh intervals, thereby reducing power usage and command bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory locations are refreshed during auto-refresh intervals, then data retention is maintained, but power consumption increases significantly
Solution Approach 1:
The patent segments the memory array into multiple banks, each with its own refresh counter. This allows selective refreshing of only active banks rather than refreshing the entire array, reducing power consumption while maintaining data retention for used memory locations.
Solution Approach 2:
The patent implements local quality by enabling different refresh behaviors for different memory banks based on their usage state. Active banks are refreshed while inactive banks are skipped, allowing each region of the memory array to have appropriate refresh characteristics based on actual demand.
2Reliability
If all memory locations are refreshed, then data integrity is maintained, but command bandwidth is wasted
Solution Approach 1:
The patent divides the refresh operation into bank-level segments, where each bank is independently managed. This segmentation enables the controller to issue refresh commands only to active banks, reducing the total number of commands and improving bandwidth efficiency while maintaining data integrity.
Solution Approach 2:
The patent implements self-service by having each memory bank maintain its own refresh counter and automatically determine when it needs refreshing. This eliminates the need for the controller to track and manage refresh operations for all banks manually, reducing command overhead and improving bandwidth efficiency.
3Reliability
If refresh operations are performed on inactive memory locations, then complete data retention is ensured, but unnecessary power is consumed
Solution Approach 1:
The patent introduces dynamic behavior by allowing the refresh counter to be incremented or decremented based on actual memory access patterns. When a bank becomes inactive, its counter is decremented, allowing the bank to be skipped in subsequent refresh cycles. This dynamic adjustment ensures power is only consumed for actively used memory locations.
Solution Approach 2:
The patent implements feedback mechanisms where the memory controller monitors access patterns to determine which banks should be refreshed. Based on this feedback, the controller adjusts refresh counter values to optimize the balance between data retention and power consumption, preventing unnecessary refresh operations on inactive banks.
Data Source
AI summary
Examples may include techniques to reduce memory cell refreshes for a memory device. These techniques include a control unit receiving a command to cause an internal refresh counter for the memory device to increment without causing one or more rows of an array of memory cells to be refreshed during an auto-refresh interval. In some examples, a memory controller has access to a refresh counter register at the memory device that may allow the memory controller to determine when to send the command that causes the internal refresh counter to increment without refreshing the one or more rows during the auto-refresh interval.