DRAM Error Correction During Row Hammer Mitigation Refresh
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Solution Overview
Problem
Existing memory systems face challenges in correcting bit flip errors during refresh operations, which can lead to increased latency and performance issues due to delayed error correction processes, especially when multiple bit flips occur beyond the capacity of error correction codes.
Innovation Solution
Incorporating an error check and scrub (ECS) procedure into refresh operations, allowing for incremental ECS across multiple refresh cycles and prioritizing poorly performing cells for more frequent checks, thereby reducing the likelihood of needing error correction during read/write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are used to correct bit flip errors, then reliability is improved, but latency increases when multiple bit flips occur beyond correction capacity
Solution Approach 1:
The patent performs error correction during refresh operations before normal read/write operations occur. By proactively detecting and correcting bit flip errors during the refresh cycle, the system prevents compounded errors from developing, thereby maintaining reliability without incurring additional latency during actual data access operations.
Solution Approach 2:
The patent implements incremental error correction that processes only a portion of code words during each refresh operation. This allows the refresh operation to complete quickly by skipping detailed correction on all code words, then continues correcting errors in subsequent refresh cycles, reducing the latency impact while still achieving comprehensive error correction.
2Reliability
If error check and scrub procedure is performed during refresh operations, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent divides the error correction process into segments that are integrated into existing refresh operations. By processing a portion of code words during each refresh and continuing in subsequent refreshes, the complex error correction task is broken into manageable segments that leverage existing refresh infrastructure, avoiding the need for a completely separate complex error correction system.
Solution Approach 2:
The patent makes the refresh operation serve multiple functions: it performs both the traditional memory refresh function and the error detection/correction function. By integrating ECS procedure into refresh operations, the system uses existing refresh circuitry and timing to accomplish error correction, eliminating the need for dedicated error correction hardware and reducing overall device complexity.
3Reliability
If incremental ECS is performed across multiple refresh cycles, then reliability is improved, but loss of time increases due to repeated checks
Solution Approach 1:
The patent performs error correction on only a portion of code words during each refresh operation rather than completing full correction on all code words in a single refresh cycle. This partial action approach allows the refresh operation to complete quickly while still making progress on error correction, with remaining corrections handled in subsequent refresh cycles, thus balancing thoroughness with time efficiency.
Data Source
AI summary
Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.