DRAM Refresh Logic Circuit Temperature Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DRAM standards face challenges in effectively implementing temperature-controlled refresh (TCR) and fine granularity refresh (FGR) modes to manage power consumption and instantaneous current reduction, particularly at low temperatures.
Innovation Solution
Incorporating a temperature sensor and refresh logic circuit in DRAM to adjust the number of row address strobe (RAS) active times in the refresh cycle time based on temperature readings for TCR mode and granularity specifications for FGR mode, allowing for automatic refresh operations and optimal power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the number of RAS active times in refresh cycle time is reduced to lower power consumption at low temperatures, then power consumption is reduced, but memory refresh coverage may be insufficient
Solution Approach 1:
The refresh logic circuit dynamically adjusts the number of RAS active times based on temperature sensing results. At lower temperatures where power consumption is more critical, the system reduces the number of RAS active times while still providing adequate refresh coverage. This dynamic adaptation resolves the contradiction by making the refresh operation flexible rather than fixed, allowing power consumption to be optimized without permanently compromising reliability.
Solution Approach 2:
The system changes the parameter of refresh cycle time by adjusting the number of RAS active times according to temperature conditions. The temperature sensor provides input that triggers parameter changes in the refresh operation, allowing the system to adapt refresh intensity to environmental conditions. This resolves the contradiction by making refresh coverage conditional on temperature, ensuring adequate protection when needed while reducing power consumption when temperatures are low.
2Reliability
If the refresh cycle time is extended to refresh more memory cell rows, then memory refresh coverage is improved, but instantaneous current increases
Solution Approach 1:
The refresh logic circuit segments the refresh operation by dividing it into a specific number of RAS active times within the refresh cycle time. Instead of performing all refresh operations simultaneously or in a fixed sequence, the system segments them based on temperature conditions and granularity settings. This segmentation allows the system to spread out current demands over time, reducing instantaneous current while still achieving comprehensive refresh coverage.
Solution Approach 2:
The system employs periodic RAS active times within the refresh cycle time, where refresh operations are distributed across multiple periodic intervals rather than concentrated in a single burst. The number of these periodic actions is adjusted based on temperature and granularity requirements. This periodic distribution resolves the contradiction by maintaining refresh coverage through repeated actions while limiting the current demand at any single moment.
3Reliability
If the number of RAS active times is increased to improve refresh coverage, then memory reliability is improved, but power consumption increases
Solution Approach 1:
The system dynamically changes the parameter of the number of RAS active times based on temperature sensing results and granularity specifications. At higher temperatures where power consumption is less critical, the system increases the number of RAS active times to improve refresh coverage. At lower temperatures, it reduces this number to conserve power. This parameter adaptation resolves the contradiction by making refresh intensity conditional rather than fixed.
Solution Approach 2:
The temperature sensor provides feedback about the operating conditions to the refresh logic circuit, which then adjusts the number of RAS active times accordingly. This feedback loop ensures that the system automatically optimizes the balance between refresh coverage and power consumption based on real-time temperature conditions, resolving the contradiction through continuous adaptation rather than static configuration.
4Power
If fine granularity refresh is implemented to reduce instantaneous current, then power management is improved, but device complexity increases
Solution Approach 1:
The refresh logic circuit is designed to perform multiple functions: it responds to temperature sensing results, processes granularity specifications from the memory controller, determines the number of RAS active times, and controls the refresh operation timing. By making this single component multi-functional, the system achieves fine granularity refresh and current management without proportionally increasing overall device complexity. The refresh logic circuit serves as a universal control element that handles multiple control parameters and operational modes.
Solution Approach 2:
The refresh logic circuit acts as an intermediary component between the temperature sensor, the memory controller, and the memory cell array. It receives input from the temperature sensor and granularity specifications, processes this information, and generates the appropriate control signals for the refresh operation. This intermediary role allows the system to implement complex fine granularity control while keeping the overall architecture manageable, as the complexity is localized to this single mediating component rather than distributed throughout the entire system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables dynamic adjustment of refresh operations to reduce power consumption and current usage, with TCR mode adapting to temperature changes and FGR mode fine-tuning refresh granularity as specified by the memory controller, thereby enhancing DRAM efficiency and performance.
Implementation Method 1
a temperature sensor, configured to sense a temperature of the DRAM
Data Source
AI summary
The invention provides a dynamic random-access memory (DRAM) and an operation method thereof. The DRAM includes a memory cell array, a temperature sensor, and a refresh logic circuit. The temperature sensor senses a temperature of the DRAM. The refresh logic circuit enters a tRFC based on a refresh command issued by a memory controller to perform an automatic refresh operation on at least one memory cell row of the memory cell array. In a temperature-controlled refresh mode, the refresh logic circuit correspondingly adjusts a number of a plurality of tRAS periods in the tRFC according to a temperature sensing result of the temperature sensor. In a fine granularity refresh mode, the refresh logic circuit correspondingly adjusts the number of the tRAS periods in the tRFC according to a granularity specified by the memory controller.