DRAM Row Hammer Control Logic with Latch Full Signal
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) systems face issues with row hammer effects, where repetitive access to a memory row leads to increased decay and data corruption in adjacent rows due to electromagnetic coupling, causing intermittent failures and data corruption, and existing solutions struggle to prevent row hammer address information from being evicted or deleted before target-refresh.
Innovation Solution
A memory device and method that includes a control logic circuit to monitor row addresses, determine row hammer addresses based on access counts, and hold up next row hammer address determination operations until the row hammer address is target-refreshed, using a latch full signal to prevent eviction and ensure storage until refresh.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If DRAM uses limited registers to control row hammers, then device complexity is reduced, but row hammer address information may be evicted or deleted before target-refresh
Solution Approach 1:
The patent segments the row hammer control function into two parts: a limited register for storing current row hammer addresses and a FIFO buffer for managing the queue of row hammer addresses. This segmentation allows the register to remain simple while the FIFO handles the complexity of address management, preventing eviction before refresh.
Solution Approach 2:
The patent introduces a FIFO buffer as an intermediary between the register and the refresh mechanism. The FIFO acts as a mediator that holds row hammer addresses temporarily, ensuring they are not lost when the register is full, thus maintaining reliability without significantly increasing overall system complexity.
2Reliability
If DRAM monitors more row hammer addresses, then reliability improves, but device complexity increases due to more registers
Solution Approach 1:
The patent implements a dynamic address management system where the FIFO buffer dynamically adjusts its content based on the current row hammer addresses being monitored. As addresses are processed and refreshed, space is freed in the FIFO, allowing new addresses to be added. This dynamic approach enables monitoring of multiple addresses without requiring a fixed large number of registers.
Solution Approach 2:
The patent employs a mechanism where row hammer addresses are discarded from the register after being processed and transferred to the FIFO for refresh. This discarding and recovering approach allows the limited register resources to be reused for new addresses, thereby enabling continuous monitoring of multiple addresses over time without permanently increasing storage requirements.
3Reliability
If DRAM performs frequent refresh operations, then data corruption is reduced, but productivity decreases due to more access interruptions
Solution Approach 1:
The patent performs preliminary identification and marking of row hammer addresses before actual data corruption occurs. By monitoring access patterns and identifying potential row hammer addresses in advance, the system can schedule refresh operations proactively, preventing data corruption rather than reacting to it. This preliminary action reduces the need for frequent emergency refresh operations.
Solution Approach 2:
The patent implements a mechanism to skip unnecessary refresh operations for addresses that are not identified as row hammer addresses. By quickly filtering and identifying only the critical addresses that require refresh, the system rushes through the monitoring and identification process, performing refresh operations only when necessary, thus minimizing access interruptions while maintaining data integrity.
Data Source
AI summary
Memory devices and methods for controlling a row hammer are provided. The memory device includes a memory cell array including a word line and a plurality of counter memory cells storing an access count value of the word line, and a control logic circuit configured to monitor a row address accessing the word line during a row hammer monitoring time frame and to determine the row address to be a row hammer address when the number of times the word line is accessed is greater than or equal to a threshold value, wherein the row hammer address is to be stored in an address storage. The control logic circuit is further configured to hold up a determination operation for a next row hammer address, based on activation of a latch full signal indicating that there is no free space to store the row hammer address in the address storage.