DRAM Row-Hammer Refresh via Dynamic Access Counting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory devices, such as DRAM, are scaled down, the row-hammer phenomenon occurs, where intense access to one word line can cause data loss in adjacent memory cells due to voltage distribution issues, leading to data corruption.
Innovation Solution
The memory device implements a row-hammer refresh operation by performing an additional refresh on word lines adjacent to those that are intensively accessed, using a memory controller to transmit row-hammer refresh commands and addresses of target rows to the memory device, which then updates access counts and selects a minimum access row for refresh.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manufacturing process is scaled down to increase integration density, then productivity and capacity are improved, but voltage distribution control deteriorates causing row-hammer phenomenon
Solution Approach 1:
The patent performs preliminary detection of row access patterns and identifies target rows that are intensively accessed before the row-hammer phenomenon can cause data loss. By proactively selecting target rows based on access count thresholds and performing refresh operations in advance, the system prevents data corruption rather than reacting after damage occurs.
Solution Approach 2:
The patent implements a feedback mechanism where the memory device monitors row access patterns, counts accesses to each word line, and uses this information to dynamically identify target rows for refresh. The memory controller receives feedback about access patterns and adjusts refresh operations accordingly, creating a closed-loop system that adapts to actual usage patterns.
2Reliability
If additional refresh operations are performed on adjacent word lines to prevent row-hammer, then data integrity is improved, but device complexity and control overhead increase
Solution Approach 1:
The memory device performs self-detection of row access patterns and self-selection of target rows using internal counters and comparison logic. The memory controller automatically generates refresh commands based on detected patterns without requiring external intervention or complex host-side logic, allowing the memory subsystem to protect itself against row-hammer attacks.
Solution Approach 2:
The patent changes the parameter of refresh timing from fixed periodic intervals to dynamic timing based on detected access patterns. By monitoring access counts and adjusting which rows receive refresh operations based on their access frequency, the system optimizes refresh resource allocation to only where needed, reducing overall control overhead while maintaining data integrity.
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
A memory device including: a memory cell array including a plurality of memory cell rows; an address buffer configured to store addresses of target rows of the plurality of memory cell rows, wherein the addresses of the target rows have been repeatedly accessed; a minimum access output circuit configured to select, when there are a plurality of rows having a same minimum access count among the target rows, any one of the plurality of rows having the same minimum access count as a minimum access row based on a selection command value, and to output an index value of the minimum access row; and a control circuit configured to output a command instructing replacement of an address corresponding to the index value of the minimum access row with an address of an access row and storage of the address of the access row in the address buffer.